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Tue, 25 Feb 2025 07:08:35 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface MIME-Version: 1.0 Date: Tue, 25 Feb 2025 12:08:17 +0000 From: "Jiaxun Yang" To: "Bibo Mao" , "QEMU devel" Cc: "Song Gao" , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= Message-Id: <23d25d66-07f4-454b-903a-f5704e1e686c@app.fastmail.com> In-Reply-To: <3fd27fd1-b976-2705-7093-aecc6ffa0438@loongson.cn> References: <20250225-la32-fixes1-v2-0-8ec68ada3dd5@flygoat.com> <3fd27fd1-b976-2705-7093-aecc6ffa0438@loongson.cn> Subject: Re: [PATCH v2 0/9] target/loongarch: LoongArch32 fixes 1 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=202.12.124.148; envelope-from=jiaxun.yang@flygoat.com; helo=fout-b5-smtp.messagingengine.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_SBL_A=0.1 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org =E5=9C=A82025=E5=B9=B42=E6=9C=8825=E6=97=A5=E4=BA=8C=E6=9C=88 =E4=B8=8A=E5= =8D=888:50=EF=BC=8Cbibo mao=E5=86=99=E9=81=93=EF=BC=9A > On 2025/2/25 =E4=B8=8A=E5=8D=888:40, Jiaxun Yang wrote: >> Hi all, >>=20 >> This series is a collection of small fixes I made to TCG for >> LoongArch32. >>=20 >> There are still many thing broken, especially on CSRs. More >> series following. However this is sufficient to boot 32bit >> kernel. > Is there any product introduction about LoongArch32 board? such as MMU=20 > type, memory type(DDR or SRAM), interrupt controller type. Sure, for LoongArch32 the most accessible board at the moment is chiplap= FPGA [1]. There are also some ASIC designs (BaiXing Project) based on chiplab. Long in short: - MMU: PG style - Mmeory: DDR - Interrupt controller: custom (Loongson-1C like) connected to CPU's int pin. Thanks [1]: https://gitee.com/loongson-edu/chiplab > > Regards > Bibo Mao >>=20 --=20 - Jiaxun