[PATCH v2 0/9] target/loongarch: LoongArch32 fixes 1

[PATCH v2 0/9] target/loongarch: LoongArch32 fixes 1

[Jiaxun Yang]

Hi all,

This series is a collection of small fixes I made to TCG for
LoongArch32.

There are still many thing broken, especially on CSRs. More
series following. However this is sufficient to boot 32bit
kernel.

Thanks for revivewing!

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
Changes in v2:
- Addressing minor review comments
- Don't create 32bit vairant, simply allow 32bit CPU on qemu-loongarch64
- Link to v1: https://lore.kernel.org/r/20241222-la32-fixes1-v1-0-8c62b7e594db@flygoat.com

---
Jiaxun Yang (9):
      target/loongarch: Enable rotr.w/rotri.w for LoongArch32
      target/loongarch: Fix address generation for gen_sc
      target/loongarch: Fix PGD CSR for LoongArch32
      target/loongarch: Perform sign extension for IOCSR reads
      target/loongarch: Use target_ulong for iocsrrd helper results
      target/loongarch: Fix some modifiers for log formatting
      target/loongarch: Use target_ulong for CSR helpers
      target/loongarch: Fix load type for gen_ll
      target/loongarch: Introduce max32 CPU type

 target/loongarch/cpu.c                             | 152 +++++++++++++++++----
 target/loongarch/helper.h                          |  22 +--
 target/loongarch/tcg/csr_helper.c                  |   2 +-
 target/loongarch/tcg/insn_trans/trans_atomic.c.inc |   8 +-
 target/loongarch/tcg/insn_trans/trans_shift.c.inc  |   4 +-
 target/loongarch/tcg/iocsr_helper.c                |  20 +--
 target/loongarch/tcg/op_helper.c                   |   4 +-
 target/loongarch/tcg/tlb_helper.c                  |   2 +-
 target/loongarch/tcg/translate.c                   |   5 +-
 9 files changed, 155 insertions(+), 64 deletions(-)
---
base-commit: 65cb7129f4160c7e07a0da107f888ec73ae96776
change-id: 20241222-la32-fixes1-368cc14d0986

Best regards,
-- 
Jiaxun Yang <jiaxun.yang@flygoat.com>

[PATCH v2 1/9] target/loongarch: Enable rotr.w/rotri.w for LoongArch32

[Jiaxun Yang]

As per "LoongArch Reference Manual Volume 1: Basic Architecture" v1.1.0,
"2.2 Table 2. Application-level basic integer instructions in LA32",
rotr.w and rotri.w is a part of LA32 basic integer instructions.

Note that those instructions are indeed not in LA32R subset, however QEMU
is not performing any check against LA32R so far.

Make it available to ALL.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
index 377307785aab4837bc181f1691632e7970a9889d..136c4c845527f0e63902a8306dcaf136dd4dd3fc 100644
--- a/target/loongarch/tcg/insn_trans/trans_shift.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_shift.c.inc
@@ -78,7 +78,7 @@ TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
 TRANS(sll_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
 TRANS(srl_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
 TRANS(sra_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
-TRANS(rotr_w, 64, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
+TRANS(rotr_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
 TRANS(rotr_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
 TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
 TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
@@ -86,5 +86,5 @@ TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
 TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
 TRANS(srai_w, ALL, gen_rri_c, EXT_NONE, EXT_NONE, gen_sari_w)
 TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
-TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
+TRANS(rotri_w, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
 TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)

-- 
2.43.0

[PATCH v2 2/9] target/loongarch: Fix address generation for gen_sc

[Jiaxun Yang]

gen_sc should use make_address_i to obtain source address
to ensure that address is properly truncated.

Another temp value is created in middle to avoid data corruption
as make_address_i may return the same memory location as src1.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
index 974bc2a70feddbf021a07b19a0859781eb3a11c4..c35f6f3ce47877ab6ad84fa2cbc50b46c0b23ad1 100644
--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
@@ -22,13 +22,12 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
     TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);
-    TCGv t0 = tcg_temp_new();
+    TCGv t0 = make_address_i(ctx, src1, a->imm);
     TCGv val = tcg_temp_new();
 
     TCGLabel *l1 = gen_new_label();
     TCGLabel *done = gen_new_label();
 
-    tcg_gen_addi_tl(t0, src1, a->imm);
     tcg_gen_brcond_tl(TCG_COND_EQ, t0, cpu_lladdr, l1);
     tcg_gen_movi_tl(dest, 0);
     tcg_gen_br(done);
@@ -36,6 +35,7 @@ static bool gen_sc(DisasContext *ctx, arg_rr_i *a, MemOp mop)
     gen_set_label(l1);
     tcg_gen_mov_tl(val, src2);
     /* generate cmpxchg */
+    t0 = tcg_temp_new();
     tcg_gen_atomic_cmpxchg_tl(t0, cpu_lladdr, cpu_llval,
                               val, ctx->mem_idx, mop);
     tcg_gen_setcond_tl(TCG_COND_EQ, dest, t0, cpu_llval);

-- 
2.43.0

[PATCH v2 3/9] target/loongarch: Fix PGD CSR for LoongArch32

[Jiaxun Yang]

As per manual, the source of PGD CSR is relevant to highest bit of
BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check
bit 31 of BADV to determine PGDH/PGDL for LoongArch32.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/csr_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_helper.c
index 15f94caefabc7722263fa46e948e21de37b4203c..821aa6af46ea2129d771fdc937eca72317cefc1e 100644
--- a/target/loongarch/tcg/csr_helper.c
+++ b/target/loongarch/tcg/csr_helper.c
@@ -26,7 +26,7 @@ target_ulong helper_csrrd_pgd(CPULoongArchState *env)
         v = env->CSR_BADV;
     }
 
-    if ((v >> 63) & 0x1) {
+    if (extract64(v, is_la64(env) ? 63 : 31, 1)) {
         v = env->CSR_PGDH;
     } else {
         v = env->CSR_PGDL;

-- 
2.43.0

Re: [PATCH v2 3/9] target/loongarch: Fix PGD CSR for LoongArch32

[Philippe Mathieu-Daudé]

On 25/2/25 01:40, Jiaxun Yang wrote:
> As per manual, the source of PGD CSR is relevant to highest bit of
> BADV. In LoongArch32, all CSRs are 32 bits only, thus we should check
> bit 31 of BADV to determine PGDH/PGDL for LoongArch32.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/csr_helper.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

[PATCH v2 4/9] target/loongarch: Perform sign extension for IOCSR reads

[Jiaxun Yang]

As per LoongArch Reference Manual - Volume 1: Basic Architecture,
4.2.2. IOCSR Access Instructions:

The reading value is described as "writes it to the general register rd
after symbolic expansion." which means it should be sign extended.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/iocsr_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/iocsr_helper.c
index b6916f53d20ca133f0000e773685cb94240bafe2..db30de2523fff01bcc8923eb12c7fca7bedca7bf 100644
--- a/target/loongarch/tcg/iocsr_helper.c
+++ b/target/loongarch/tcg/iocsr_helper.c
@@ -17,20 +17,20 @@
 
 uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
 {
-    return address_space_ldub(env->address_space_iocsr, r_addr,
-                              GET_MEMTXATTRS(env), NULL);
+    return (int8_t)address_space_ldub(env->address_space_iocsr, r_addr,
+                                      GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
 {
-    return address_space_lduw(env->address_space_iocsr, r_addr,
-                              GET_MEMTXATTRS(env), NULL);
+    return (int16_t)address_space_lduw(env->address_space_iocsr, r_addr,
+                                       GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
 {
-    return address_space_ldl(env->address_space_iocsr, r_addr,
-                             GET_MEMTXATTRS(env), NULL);
+    return (int32_t)address_space_ldl(env->address_space_iocsr, r_addr,
+                                      GET_MEMTXATTRS(env), NULL);
 }
 
 uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)

-- 
2.43.0

[PATCH v2 5/9] target/loongarch: Use target_ulong for iocsrrd helper results

[Jiaxun Yang]

Those results are all targeting TCGv values, which means they should
be in target_ulong type.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/helper.h           | 8 ++++----
 target/loongarch/tcg/iocsr_helper.c | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index b3b64a021536255a3f9decfc10ff61fe8380e2ae..409d93a5b0808f0e32b8c0e2e17cebac9feaf8ed 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -104,10 +104,10 @@ DEF_HELPER_2(csrwr_estat, i64, env, tl)
 DEF_HELPER_2(csrwr_asid, i64, env, tl)
 DEF_HELPER_2(csrwr_tcfg, i64, env, tl)
 DEF_HELPER_2(csrwr_ticlr, i64, env, tl)
-DEF_HELPER_2(iocsrrd_b, i64, env, tl)
-DEF_HELPER_2(iocsrrd_h, i64, env, tl)
-DEF_HELPER_2(iocsrrd_w, i64, env, tl)
-DEF_HELPER_2(iocsrrd_d, i64, env, tl)
+DEF_HELPER_2(iocsrrd_b, tl, env, tl)
+DEF_HELPER_2(iocsrrd_h, tl, env, tl)
+DEF_HELPER_2(iocsrrd_w, tl, env, tl)
+DEF_HELPER_2(iocsrrd_d, tl, env, tl)
 DEF_HELPER_3(iocsrwr_b, void, env, tl, tl)
 DEF_HELPER_3(iocsrwr_h, void, env, tl, tl)
 DEF_HELPER_3(iocsrwr_w, void, env, tl, tl)
diff --git a/target/loongarch/tcg/iocsr_helper.c b/target/loongarch/tcg/iocsr_helper.c
index db30de2523fff01bcc8923eb12c7fca7bedca7bf..23d819de0ef9790eb82741f1e8a0e20dc139bf4b 100644
--- a/target/loongarch/tcg/iocsr_helper.c
+++ b/target/loongarch/tcg/iocsr_helper.c
@@ -15,25 +15,25 @@
 #define GET_MEMTXATTRS(cas) \
         ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index})
 
-uint64_t helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
+target_ulong helper_iocsrrd_b(CPULoongArchState *env, target_ulong r_addr)
 {
     return (int8_t)address_space_ldub(env->address_space_iocsr, r_addr,
                                       GET_MEMTXATTRS(env), NULL);
 }
 
-uint64_t helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
+target_ulong helper_iocsrrd_h(CPULoongArchState *env, target_ulong r_addr)
 {
     return (int16_t)address_space_lduw(env->address_space_iocsr, r_addr,
                                        GET_MEMTXATTRS(env), NULL);
 }
 
-uint64_t helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
+target_ulong helper_iocsrrd_w(CPULoongArchState *env, target_ulong r_addr)
 {
     return (int32_t)address_space_ldl(env->address_space_iocsr, r_addr,
                                       GET_MEMTXATTRS(env), NULL);
 }
 
-uint64_t helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
+target_ulong helper_iocsrrd_d(CPULoongArchState *env, target_ulong r_addr)
 {
     return address_space_ldq(env->address_space_iocsr, r_addr,
                              GET_MEMTXATTRS(env), NULL);

-- 
2.43.0

[PATCH v2 6/9] target/loongarch: Fix some modifiers for log formatting

[Jiaxun Yang]

target_ulong -> TARGET_FMT_ld
vaddr -> VADDR_PRIx
uint32_t -> PRIx32

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
 target/loongarch/tcg/tlb_helper.c                  | 2 +-
 target/loongarch/tcg/translate.c                   | 5 ++---
 3 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
index c35f6f3ce47877ab6ad84fa2cbc50b46c0b23ad1..8584441b543712af8a56aa234c90fd6370c8df01 100644
--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
@@ -56,7 +56,7 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a,
     if (a->rd != 0 && (a->rj == a->rd || a->rk == a->rd)) {
         qemu_log_mask(LOG_GUEST_ERROR,
                       "Warning: source register overlaps destination register"
-                      "in atomic insn at pc=0x" TARGET_FMT_lx "\n",
+                      "in atomic insn at pc=0x%016"VADDR_PRIx"\n",
                       ctx->base.pc_next - 4);
         return false;
     }
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index 97f38fc391338ba4b76115b142fa76d89e45cd62..a1426b46f36c99e300ab924cb487875ec21ab226 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -517,7 +517,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
 
     if (unlikely((level == 0) || (level > 4))) {
         qemu_log_mask(LOG_GUEST_ERROR,
-                      "Attepted LDDIR with level %"PRId64"\n", level);
+                      "Attepted LDDIR with level "TARGET_FMT_ld"\n", level);
         return base;
     }
 
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index 1fca4afc731c048816618d87610a0cc0fe7579b1..3939670e18d01bd9fc08861532166882fbd3f890 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -287,9 +287,8 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
     ctx->opcode = translator_ldl(cpu_env(cs), &ctx->base, ctx->base.pc_next);
 
     if (!decode(ctx, ctx->opcode)) {
-        qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. "
-                      TARGET_FMT_lx ": 0x%x\n",
-                      ctx->base.pc_next, ctx->opcode);
+        qemu_log_mask(LOG_UNIMP, "Error: unknown opcode. %016"VADDR_PRIx
+                      ": 0x%08"PRIx32"\n", ctx->base.pc_next, ctx->opcode);
         generate_exception(ctx, EXCCODE_INE);
     }
 

-- 
2.43.0

Re: [PATCH v2 6/9] target/loongarch: Fix some modifiers for log formatting

[Philippe Mathieu-Daudé]

On 25/2/25 01:40, Jiaxun Yang wrote:
> target_ulong -> TARGET_FMT_ld
> vaddr -> VADDR_PRIx
> uint32_t -> PRIx32
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>   target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
>   target/loongarch/tcg/tlb_helper.c                  | 2 +-
>   target/loongarch/tcg/translate.c                   | 5 ++---
>   3 files changed, 4 insertions(+), 5 deletions(-)


> diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
> index 97f38fc391338ba4b76115b142fa76d89e45cd62..a1426b46f36c99e300ab924cb487875ec21ab226 100644
> --- a/target/loongarch/tcg/tlb_helper.c
> +++ b/target/loongarch/tcg/tlb_helper.c
> @@ -517,7 +517,7 @@ target_ulong helper_lddir(CPULoongArchState *env, target_ulong base,
>   
>       if (unlikely((level == 0) || (level > 4))) {
>           qemu_log_mask(LOG_GUEST_ERROR,
> -                      "Attepted LDDIR with level %"PRId64"\n", level);
> +                      "Attepted LDDIR with level "TARGET_FMT_ld"\n", level);

"Attempted"?

>           return base;
>       }

[PATCH v2 7/9] target/loongarch: Use target_ulong for CSR helpers

[Jiaxun Yang]

All CSRs are meant to be target_ulong wide in our setting.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/helper.h        | 14 +++++++-------
 target/loongarch/tcg/op_helper.c |  4 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 409d93a5b0808f0e32b8c0e2e17cebac9feaf8ed..a608754b7f52689da9e9f4da1cef68d5af72f2ed 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -97,13 +97,13 @@ DEF_HELPER_1(rdtime_d, i64, env)
 
 #ifndef CONFIG_USER_ONLY
 /* CSRs helper */
-DEF_HELPER_1(csrrd_pgd, i64, env)
-DEF_HELPER_1(csrrd_cpuid, i64, env)
-DEF_HELPER_1(csrrd_tval, i64, env)
-DEF_HELPER_2(csrwr_estat, i64, env, tl)
-DEF_HELPER_2(csrwr_asid, i64, env, tl)
-DEF_HELPER_2(csrwr_tcfg, i64, env, tl)
-DEF_HELPER_2(csrwr_ticlr, i64, env, tl)
+DEF_HELPER_1(csrrd_pgd, tl, env)
+DEF_HELPER_1(csrrd_cpuid, tl, env)
+DEF_HELPER_1(csrrd_tval, tl, env)
+DEF_HELPER_2(csrwr_estat, tl, env, tl)
+DEF_HELPER_2(csrwr_asid, tl, env, tl)
+DEF_HELPER_2(csrwr_tcfg, tl, env, tl)
+DEF_HELPER_2(csrwr_ticlr, tl, env, tl)
 DEF_HELPER_2(iocsrrd_b, tl, env, tl)
 DEF_HELPER_2(iocsrrd_h, tl, env, tl)
 DEF_HELPER_2(iocsrrd_w, tl, env, tl)
diff --git a/target/loongarch/tcg/op_helper.c b/target/loongarch/tcg/op_helper.c
index b17208e5b962f2191b2afa60181bff311d618bba..c9d7e84e7ec9000bab655366bdf6ed8aaa4fd080 100644
--- a/target/loongarch/tcg/op_helper.c
+++ b/target/loongarch/tcg/op_helper.c
@@ -61,7 +61,7 @@ void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk)
     }
 }
 
-target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
+target_ulong helper_crc32(target_ulong val, target_ulong m, target_ulong sz)
 {
     uint8_t buf[8];
     target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);
@@ -71,7 +71,7 @@ target_ulong helper_crc32(target_ulong val, target_ulong m, uint64_t sz)
     return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff);
 }
 
-target_ulong helper_crc32c(target_ulong val, target_ulong m, uint64_t sz)
+target_ulong helper_crc32c(target_ulong val, target_ulong m, target_ulong sz)
 {
     uint8_t buf[8];
     target_ulong mask = ((sz * 8) == 64) ? -1ULL : ((1ULL << (sz * 8)) - 1);

-- 
2.43.0

[PATCH v2 8/9] target/loongarch: Fix load type for gen_ll

[Jiaxun Yang]

gen_ll should use tcg_gen_qemu_ld_tl to load t1, as t1 is
in TCGv which means it should be a tl type value.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
index 8584441b543712af8a56aa234c90fd6370c8df01..138bcb3e9999b2c186057c658a019136311f1b82 100644
--- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc
@@ -9,7 +9,7 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
     TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
     TCGv t0 = make_address_i(ctx, src1, a->imm);
 
-    tcg_gen_qemu_ld_i64(t1, t0, ctx->mem_idx, mop);
+    tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, mop);
     tcg_gen_st_tl(t0, tcg_env, offsetof(CPULoongArchState, lladdr));
     tcg_gen_st_tl(t1, tcg_env, offsetof(CPULoongArchState, llval));
     gen_set_gpr(a->rd, t1, EXT_NONE);

-- 
2.43.0

[PATCH v2 9/9] target/loongarch: Introduce max32 CPU type

[Jiaxun Yang]

Introduce max32 CPU type as it's necessary to demonstrate all
features we have in LA32.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 target/loongarch/cpu.c | 152 +++++++++++++++++++++++++++++++++++++++----------
 1 file changed, 122 insertions(+), 30 deletions(-)

diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index f5bc8720d1fc1b28950ee02de5ae6cce86fc6a96..43a18871ea88a92c72a3b3f1493d760df6f0df20 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -375,6 +375,126 @@ static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
     return MMU_DA_IDX;
 }
 
+static void loongarch_la132_initfn(Object *obj)
+{
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    CPULoongArchState *env = &cpu->env;
+
+    int i;
+
+    for (i = 0; i < 21; i++) {
+        env->cpucfg[i] = 0x0;
+    }
+
+    cpu->dtb_compatible = "loongarch,Loongson-1C103";
+    env->cpucfg[0] = 0x148042;  /* PRID */
+
+    uint32_t data = 0;
+    data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
+    data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
+    data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
+    data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
+    data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
+    data = FIELD_DP32(data, CPUCFG1, UAL, 1);
+    data = FIELD_DP32(data, CPUCFG1, RI, 0);
+    data = FIELD_DP32(data, CPUCFG1, EP, 0);
+    data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
+    data = FIELD_DP32(data, CPUCFG1, HP, 1);
+    data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
+    env->cpucfg[1] = data;
+}
+
+static void loongarch_max32_initfn(Object *obj)
+{
+    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+    CPULoongArchState *env = &cpu->env;
+    int i;
+
+    for (i = 0; i < 21; i++) {
+        env->cpucfg[i] = 0x0;
+    }
+
+    cpu->dtb_compatible = "loongarch,la32";
+    env->cpucfg[0] = 0x148042;  /* PRID */
+
+    uint32_t data = 0;
+    data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
+    data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
+    data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
+    data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
+    data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
+    data = FIELD_DP32(data, CPUCFG1, UAL, 1);
+    data = FIELD_DP32(data, CPUCFG1, HP, 1);
+    data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
+    env->cpucfg[1] = data;
+
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG2, FP, 1);
+    data = FIELD_DP32(data, CPUCFG2, FP_SP, 1);
+    data = FIELD_DP32(data, CPUCFG2, FP_DP, 1);
+    data = FIELD_DP32(data, CPUCFG2, FP_VER, 1);
+    data = FIELD_DP32(data, CPUCFG2, LLFTP, 1);
+    data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
+    env->cpucfg[2] = data;
+
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG3, CCDMA, 1);
+    data = FIELD_DP32(data, CPUCFG3, ITLBHMC, 1);
+    data = FIELD_DP32(data, CPUCFG3, ICHMC, 1);
+    env->cpucfg[3] = data;
+
+    env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */
+
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1);
+    data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1);
+    env->cpucfg[5] = data;
+
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1);
+    data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1);
+    data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1);
+    data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1);
+    data = FIELD_DP32(data, CPUCFG16, L2_IUINCL, 1);
+    env->cpucfg[16] = data;
+
+    /* 16K L1I */
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3);
+    data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 7);
+    data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 5);
+    env->cpucfg[17] = data;
+
+    /* 16K L1D */
+    data = 0;
+    data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3);
+    data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 7);
+    data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 5);
+    env->cpucfg[18] = data;
+
+    data = 0;
+    /* 128K L2 */
+    data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 7);
+    data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 9);
+    data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 5);
+    env->cpucfg[19] = data;
+
+    env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
+
+    env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, SAVE_NUM, 8);
+    env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, TIMER_BITS, 31);
+    env->CSR_PRCFG1 = FIELD_DP64(env->CSR_PRCFG1, CSR_PRCFG1, VSMAX, 0);
+
+    env->CSR_PRCFG2 = 0x3ffff000;
+
+    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
+    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
+    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
+    env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
+
+    loongarch_cpu_post_init(obj);
+}
+
 static void loongarch_la464_initfn(Object *obj)
 {
     LoongArchCPU *cpu = LOONGARCH_CPU(obj);
@@ -473,35 +593,6 @@ static void loongarch_la464_initfn(Object *obj)
     loongarch_cpu_post_init(obj);
 }
 
-static void loongarch_la132_initfn(Object *obj)
-{
-    LoongArchCPU *cpu = LOONGARCH_CPU(obj);
-    CPULoongArchState *env = &cpu->env;
-
-    int i;
-
-    for (i = 0; i < 21; i++) {
-        env->cpucfg[i] = 0x0;
-    }
-
-    cpu->dtb_compatible = "loongarch,Loongson-1C103";
-    env->cpucfg[0] = 0x148042;  /* PRID */
-
-    uint32_t data = 0;
-    data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
-    data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
-    data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
-    data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
-    data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
-    data = FIELD_DP32(data, CPUCFG1, UAL, 1);
-    data = FIELD_DP32(data, CPUCFG1, RI, 0);
-    data = FIELD_DP32(data, CPUCFG1, EP, 0);
-    data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
-    data = FIELD_DP32(data, CPUCFG1, HP, 1);
-    data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
-    env->cpucfg[1] = data;
-}
-
 static void loongarch_max_initfn(Object *obj)
 {
     /* '-cpu max' for TCG: we use cpu la464. */
@@ -916,8 +1007,9 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
         .abstract = true,
         .class_init = loongarch64_cpu_class_init,
     },
-    DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
     DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn),
+    DEFINE_LOONGARCH_CPU_TYPE(32, "max32", loongarch_max32_initfn),
+    DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn),
     DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn),
 };
 

-- 
2.43.0

Re: [PATCH v2 0/9] target/loongarch: LoongArch32 fixes 1

[bibo mao]

On 2025/2/25 上午8:40, Jiaxun Yang wrote:
> Hi all,
> 
> This series is a collection of small fixes I made to TCG for
> LoongArch32.
> 
> There are still many thing broken, especially on CSRs. More
> series following. However this is sufficient to boot 32bit
> kernel.
Is there any product introduction about LoongArch32 board? such as MMU 
type, memory type(DDR or SRAM), interrupt controller type.

Regards
Bibo Mao
> 
> Thanks for revivewing!
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
> Changes in v2:
> - Addressing minor review comments
> - Don't create 32bit vairant, simply allow 32bit CPU on qemu-loongarch64
> - Link to v1: https://lore.kernel.org/r/20241222-la32-fixes1-v1-0-8c62b7e594db@flygoat.com
> 
> ---
> Jiaxun Yang (9):
>        target/loongarch: Enable rotr.w/rotri.w for LoongArch32
>        target/loongarch: Fix address generation for gen_sc
>        target/loongarch: Fix PGD CSR for LoongArch32
>        target/loongarch: Perform sign extension for IOCSR reads
>        target/loongarch: Use target_ulong for iocsrrd helper results
>        target/loongarch: Fix some modifiers for log formatting
>        target/loongarch: Use target_ulong for CSR helpers
>        target/loongarch: Fix load type for gen_ll
>        target/loongarch: Introduce max32 CPU type
> 
>   target/loongarch/cpu.c                             | 152 +++++++++++++++++----
>   target/loongarch/helper.h                          |  22 +--
>   target/loongarch/tcg/csr_helper.c                  |   2 +-
>   target/loongarch/tcg/insn_trans/trans_atomic.c.inc |   8 +-
>   target/loongarch/tcg/insn_trans/trans_shift.c.inc  |   4 +-
>   target/loongarch/tcg/iocsr_helper.c                |  20 +--
>   target/loongarch/tcg/op_helper.c                   |   4 +-
>   target/loongarch/tcg/tlb_helper.c                  |   2 +-
>   target/loongarch/tcg/translate.c                   |   5 +-
>   9 files changed, 155 insertions(+), 64 deletions(-)
> ---
> base-commit: 65cb7129f4160c7e07a0da107f888ec73ae96776
> change-id: 20241222-la32-fixes1-368cc14d0986
> 
> Best regards,
> 

Re: [PATCH v2 0/9] target/loongarch: LoongArch32 fixes 1

[Jiaxun Yang]

在2025年2月25日二月 上午8:50，bibo mao写道：
> On 2025/2/25 上午8:40, Jiaxun Yang wrote:
>> Hi all,
>> 
>> This series is a collection of small fixes I made to TCG for
>> LoongArch32.
>> 
>> There are still many thing broken, especially on CSRs. More
>> series following. However this is sufficient to boot 32bit
>> kernel.
> Is there any product introduction about LoongArch32 board? such as MMU 
> type, memory type(DDR or SRAM), interrupt controller type.

Sure, for LoongArch32 the most accessible board at the moment is chiplap FPGA [1].

There are also some ASIC designs (BaiXing Project) based on chiplab.

Long in short:

- MMU: PG style
- Mmeory: DDR
- Interrupt controller: custom (Loongson-1C like) connected to CPU's
                        int pin.

Thanks

[1]: https://gitee.com/loongson-edu/chiplab

>
> Regards
> Bibo Mao
>> 


-- 
- Jiaxun

Re: [PATCH v2 0/9] target/loongarch: LoongArch32 fixes 1

[bibo mao]

On 2025/2/25 下午8:08, Jiaxun Yang wrote:
> 
> 
> 在2025年2月25日二月 上午8:50，bibo mao写道：
>> On 2025/2/25 上午8:40, Jiaxun Yang wrote:
>>> Hi all,
>>>
>>> This series is a collection of small fixes I made to TCG for
>>> LoongArch32.
>>>
>>> There are still many thing broken, especially on CSRs. More
>>> series following. However this is sufficient to boot 32bit
>>> kernel.
>> Is there any product introduction about LoongArch32 board? such as MMU
>> type, memory type(DDR or SRAM), interrupt controller type.
> 
> Sure, for LoongArch32 the most accessible board at the moment is chiplap FPGA [1].
> 
> There are also some ASIC designs (BaiXing Project) based on chiplab.
> 
> Long in short:
> 
> - MMU: PG style
> - Mmeory: DDR
> - Interrupt controller: custom (Loongson-1C like) connected to CPU's
>                          int pin.
Thanks for the information, Would you like to emulate LoongArch32 
chiplap FPGA board in qemu side or other LoongArch32 boards?

Regards
Bibo Mao
> 
> Thanks
> 
> [1]: https://gitee.com/loongson-edu/chiplab
> 
>>
>> Regards
>> Bibo Mao
>>>
> 
> 

Re: [PATCH v2 0/9] target/loongarch: LoongArch32 fixes 1

[Jiaxun Yang]

在2025年2月25日二月 下午12:33，bibo mao写道：
> On 2025/2/25 下午8:08, Jiaxun Yang wrote:
>> 
>> 
>> 在2025年2月25日二月 上午8:50，bibo mao写道：
>>> On 2025/2/25 上午8:40, Jiaxun Yang wrote:
>>>> Hi all,
>>>>
>>>> This series is a collection of small fixes I made to TCG for
>>>> LoongArch32.
>>>>
>>>> There are still many thing broken, especially on CSRs. More
>>>> series following. However this is sufficient to boot 32bit
>>>> kernel.
>>> Is there any product introduction about LoongArch32 board? such as MMU
>>> type, memory type(DDR or SRAM), interrupt controller type.
>> 
>> Sure, for LoongArch32 the most accessible board at the moment is chiplap FPGA [1].
>> 
>> There are also some ASIC designs (BaiXing Project) based on chiplab.
>> 
>> Long in short:
>> 
>> - MMU: PG style
>> - Mmeory: DDR
>> - Interrupt controller: custom (Loongson-1C like) connected to CPU's
>>                          int pin.
> Thanks for the information, Would you like to emulate LoongArch32 
> chiplap FPGA board in qemu side or other LoongArch32 boards?

My plan is to use current virt machine (with EXTIOI and so on) for
LoongArch32, it is trivial to bring up in kernel and give us a lot more
flexibility rather than emulating an actual board.

Thanks
- Jiaxun

>
> Regards
> Bibo Mao
>> 
>> Thanks
>> 
>> [1]: https://gitee.com/loongson-edu/chiplab
>> 
>>>
>>> Regards
>>> Bibo Mao
>>>>
>> 
>>

-- 
- Jiaxun

Re: [PATCH v2 0/9] target/loongarch: LoongArch32 fixes 1

[bibo mao]

On 2025/2/27 下午6:44, Jiaxun Yang wrote:
> 
> 
> 在2025年2月25日二月 下午12:33，bibo mao写道：
>> On 2025/2/25 下午8:08, Jiaxun Yang wrote:
>>>
>>>
>>> 在2025年2月25日二月 上午8:50，bibo mao写道：
>>>> On 2025/2/25 上午8:40, Jiaxun Yang wrote:
>>>>> Hi all,
>>>>>
>>>>> This series is a collection of small fixes I made to TCG for
>>>>> LoongArch32.
>>>>>
>>>>> There are still many thing broken, especially on CSRs. More
>>>>> series following. However this is sufficient to boot 32bit
>>>>> kernel.
>>>> Is there any product introduction about LoongArch32 board? such as MMU
>>>> type, memory type(DDR or SRAM), interrupt controller type.
>>>
>>> Sure, for LoongArch32 the most accessible board at the moment is chiplap FPGA [1].
>>>
>>> There are also some ASIC designs (BaiXing Project) based on chiplab.
>>>
>>> Long in short:
>>>
>>> - MMU: PG style
>>> - Mmeory: DDR
>>> - Interrupt controller: custom (Loongson-1C like) connected to CPU's
>>>                           int pin.
>> Thanks for the information, Would you like to emulate LoongArch32
>> chiplap FPGA board in qemu side or other LoongArch32 boards?
> 
> My plan is to use current virt machine (with EXTIOI and so on) for
> LoongArch32, it is trivial to bring up in kernel and give us a lot more
> flexibility rather than emulating an actual board.
virt machine is mainly for kvm board. If it is used as LoongArch32 
board, there is no much benefit to add bunch of code in kernel and qemu 
to emulate non-exist board, on the contrast it is hard to maintain.

In LoongArch community There are many cases posting code in one time, 
disappear and lose maintenance :(

Regards
Bibo MAo

> 
> Thanks
> - Jiaxun
> 
>>
>> Regards
>> Bibo Mao
>>>
>>> Thanks
>>>
>>> [1]: https://gitee.com/loongson-edu/chiplab
>>>
>>>>
>>>> Regards
>>>> Bibo Mao
>>>>>
>>>
>>>
> 

Re: [PATCH v2 0/9] target/loongarch: LoongArch32 fixes 1

[Jiaxun Yang]

在2025年2月27日二月 下午12:21，bibo mao写道：
[...]
>>>>                           int pin.
>>> Thanks for the information, Would you like to emulate LoongArch32
>>> chiplap FPGA board in qemu side or other LoongArch32 boards?
>> 
>> My plan is to use current virt machine (with EXTIOI and so on) for
>> LoongArch32, it is trivial to bring up in kernel and give us a lot more
>> flexibility rather than emulating an actual board.
> virt machine is mainly for kvm board. If it is used as LoongArch32 
> board, there is no much benefit to add bunch of code in kernel and qemu 
> to emulate non-exist board, on the contrast it is hard to maintain.

Actually, it's 8 lines of code machine level code in my local tree to bring
up. Adding a new board will increase maintain burden as well. Also to note
that LoongArch32 TCG work is also for qemu user.

riscv32, arm32 are all sharing same virt board as well. QEMU is not only
serving KVM but also other users trying to evaluate and test on the platform.

For kernel drivers are already here, still, just a couple of Kconfig changes,
you can preview here [1].

>
> In LoongArch community There are many cases posting code in one time, 
> disappear and lose maintenance :(

Yep, for hobbyists it's hard to sustain our effort :-( we are all trying
our best to contribute. I can potentially spare more time in Q2 to make
everything work.

Thanks

[1]: https://github.com/FlyGoat/linux/tree/b4/la32
-- 
- Jiaxun