From: Richard Henderson <richard.henderson@linaro.org>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-devel@nongnu.org
Cc: Huacai Chen <chenhuacai@kernel.org>, Paul Burton <paulburton@kernel.org>
Subject: Re: [PULL 00/17] MIPS patches for 2021-10-18
Date: Mon, 18 Oct 2021 11:41:59 -0700 [thread overview]
Message-ID: <23ffd3b9-4210-33f5-cada-b1dafe4c838e@linaro.org> (raw)
In-Reply-To: <20211017225245.2618892-1-f4bug@amsat.org>
On 10/17/21 3:52 PM, Philippe Mathieu-Daudé wrote:
> The following changes since commit c148a0572130ff485cd2249fbdd1a3260d5e10a4:
>
> Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211016' into staging (2021-10-16 11:16:28 -0700)
>
> are available in the Git repository at:
>
> https://github.com/philmd/qemu.git tags/mips-20211018
>
> for you to fetch changes up to 2792cf20ca7eed0e354a0ed731422411faca4908:
>
> via-ide: Avoid using isa_get_irq() (2021-10-18 00:41:36 +0200)
>
> ----------------------------------------------------------------
> MIPS patches queue
>
> Hardware emulation:
> - Generate FDT blob for Boston machine (Jiaxun)
> - VIA chipset cleanups (Zoltan)
>
> TCG:
> - Use tcg_constant() in Compact branch and MSA opcodes
> - Restrict nanoMIPS DSP MULT[U] opcode accumulator to Rel6
> - Fix DEXTRV_S.H DSP opcode
> - Remove unused TCG temporary for some DSP opcodes
>
> ----------------------------------------------------------------
>
> BALATON Zoltan (4):
> via-ide: Set user_creatable to false
> vt82c686: Move common code to via_isa_realize
> vt82c686: Add a method to VIA_ISA to raise ISA interrupts
> via-ide: Avoid using isa_get_irq()
>
> Jiaxun Yang (3):
> hw/mips/boston: Massage memory map information
> hw/mips/boston: Allow loading elf kernel and dtb
> hw/mips/boston: Add FDT generator
>
> Philippe Mathieu-Daudé (10):
> target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6
> target/mips: Remove unused register from MSA 2R/2RF instruction format
> target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
> target/mips: Use tcg_constant_i32() in gen_msa_2rf()
> target/mips: Use tcg_constant_i32() in gen_msa_2r()
> target/mips: Use tcg_constant_i32() in gen_msa_3rf()
> target/mips: Use explicit extract32() calls in gen_msa_i5()
> target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()
> target/mips: Fix DEXTRV_S.H DSP opcode
> target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()
>
> include/hw/isa/vt82c686.h | 4 +
> hw/ide/via.c | 7 +-
> hw/isa/vt82c686.c | 75 +++--
> hw/mips/boston.c | 371 +++++++++++++++++++++--
> target/mips/tcg/msa_translate.c | 51 ++--
> target/mips/tcg/translate.c | 11 +-
> target/mips/tcg/nanomips_translate.c.inc | 6 +
> 7 files changed, 415 insertions(+), 110 deletions(-)
Applied, thanks.
r~
prev parent reply other threads:[~2021-10-18 18:43 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-17 22:52 [PULL 00/17] MIPS patches for 2021-10-18 Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 01/17] target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6 Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 02/17] hw/mips/boston: Massage memory map information Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 03/17] hw/mips/boston: Allow loading elf kernel and dtb Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 04/17] hw/mips/boston: Add FDT generator Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 05/17] target/mips: Remove unused register from MSA 2R/2RF instruction format Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 06/17] target/mips: Use tcg_constant_i32() in gen_msa_elm_df() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 07/17] target/mips: Use tcg_constant_i32() in gen_msa_2rf() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 08/17] target/mips: Use tcg_constant_i32() in gen_msa_2r() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 09/17] target/mips: Use tcg_constant_i32() in gen_msa_3rf() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 10/17] target/mips: Use explicit extract32() calls in gen_msa_i5() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 11/17] target/mips: Use tcg_constant_tl() in gen_compute_compact_branch() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 12/17] target/mips: Fix DEXTRV_S.H DSP opcode Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 13/17] target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn() Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 14/17] via-ide: Set user_creatable to false Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 15/17] vt82c686: Move common code to via_isa_realize Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 16/17] vt82c686: Add a method to VIA_ISA to raise ISA interrupts Philippe Mathieu-Daudé
2021-10-17 22:52 ` [PULL 17/17] via-ide: Avoid using isa_get_irq() Philippe Mathieu-Daudé
2021-10-18 18:41 ` Richard Henderson [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=23ffd3b9-4210-33f5-cada-b1dafe4c838e@linaro.org \
--to=richard.henderson@linaro.org \
--cc=chenhuacai@kernel.org \
--cc=f4bug@amsat.org \
--cc=paulburton@kernel.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).