From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36673) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c5DZc-0008So-1b for qemu-devel@nongnu.org; Fri, 11 Nov 2016 10:17:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c5DZX-00060w-2Z for qemu-devel@nongnu.org; Fri, 11 Nov 2016 10:16:58 -0500 References: <1478798481-25030-1-git-send-email-drjones@redhat.com> <1478798481-25030-7-git-send-email-drjones@redhat.com> <87vavu6pc7.fsf@linaro.org> From: Andre Przywara Message-ID: <2400d95c-02c3-5621-8cc1-32a61d3795e8@arm.com> Date: Fri, 11 Nov 2016 15:17:25 +0000 MIME-Version: 1.0 In-Reply-To: <87vavu6pc7.fsf@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [kvm-unit-tests PATCH v5 06/11] arm/arm64: add initial gicv2 support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Andrew Jones Cc: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, qemu-devel@nongnu.org, qemu-arm@nongnu.org, pbonzini@redhat.com, peter.maydell@linaro.org, marc.zyngier@arm.com, eric.auger@redhat.com, christoffer.dall@linaro.org Hi, On 11/11/16 14:52, Alex Benn=C3=A9e wrote: >=20 > Andrew Jones writes: >=20 >> Add some gicv2 support. This just adds init and enable >> functions, allowing unit tests to start messing with it. >> >> Signed-off-by: Andrew Jones >> >> --- >> v5: share/use only the modern register names [Andre] >> v4: >> - only take defines from kernel we need now [Andre] >> - moved defines to asm/gic.h so they'll be shared with v3 [drew] >> - simplify enable by not caring if we reinit the distributor [drew] >> - init all GICD_INT_DEF_PRI_X4 registers [Eric] >> --- >> arm/Makefile.common | 1 + >> lib/arm/asm/gic-v2.h | 34 ++++++++++++++++++++++ >> lib/arm/asm/gic.h | 37 ++++++++++++++++++++++++ >> lib/arm/gic.c | 76 +++++++++++++++++++++++++++++++++++++++++= +++++++++ >> lib/arm64/asm/gic-v2.h | 1 + >> lib/arm64/asm/gic.h | 1 + >> 6 files changed, 150 insertions(+) >> create mode 100644 lib/arm/asm/gic-v2.h >> create mode 100644 lib/arm/asm/gic.h >> create mode 100644 lib/arm/gic.c >> create mode 100644 lib/arm64/asm/gic-v2.h >> create mode 100644 lib/arm64/asm/gic.h >> >> diff --git a/arm/Makefile.common b/arm/Makefile.common >> index ccb554d9251a..41239c37e092 100644 >> --- a/arm/Makefile.common >> +++ b/arm/Makefile.common >> @@ -42,6 +42,7 @@ cflatobjs +=3D lib/arm/mmu.o >> cflatobjs +=3D lib/arm/bitops.o >> cflatobjs +=3D lib/arm/psci.o >> cflatobjs +=3D lib/arm/smp.o >> +cflatobjs +=3D lib/arm/gic.o >> >> libeabi =3D lib/arm/libeabi.a >> eabiobjs =3D lib/arm/eabi_compat.o >> diff --git a/lib/arm/asm/gic-v2.h b/lib/arm/asm/gic-v2.h >> new file mode 100644 >> index 000000000000..c2d5fecd4886 >> --- /dev/null >> +++ b/lib/arm/asm/gic-v2.h >> @@ -0,0 +1,34 @@ >> +/* >> + * All GIC* defines are lifted from include/linux/irqchip/arm-gic.h >> + * >> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones >> + * >> + * This work is licensed under the terms of the GNU LGPL, version 2. >> + */ >> +#ifndef _ASMARM_GIC_V2_H_ >> +#define _ASMARM_GIC_V2_H_ >> + >> +#ifndef _ASMARM_GIC_H_ >> +#error Do not directly include . Include >> +#endif >> + >> +#define GICD_ENABLE 0x1 >> +#define GICC_ENABLE 0x1 >> + >> +#ifndef __ASSEMBLY__ >> + >> +struct gicv2_data { >> + void *dist_base; >> + void *cpu_base; >> + unsigned int irq_nr; >> +}; >> +extern struct gicv2_data gicv2_data; >> + >> +#define gicv2_dist_base() (gicv2_data.dist_base) >> +#define gicv2_cpu_base() (gicv2_data.cpu_base) >> + >> +extern int gicv2_init(void); >> +extern void gicv2_enable_defaults(void); >> + >> +#endif /* !__ASSEMBLY__ */ >> +#endif /* _ASMARM_GIC_V2_H_ */ >> diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h >> new file mode 100644 >> index 000000000000..d44e47bcf404 >> --- /dev/null >> +++ b/lib/arm/asm/gic.h >> @@ -0,0 +1,37 @@ >> +/* >> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones >> + * >> + * This work is licensed under the terms of the GNU LGPL, version 2. >> + */ >> +#ifndef _ASMARM_GIC_H_ >> +#define _ASMARM_GIC_H_ >> + >> +#include >> + >> +#define GICD_CTLR 0x0000 >> +#define GICD_TYPER 0x0004 >> +#define GICD_ISENABLER 0x0100 >> +#define GICD_IPRIORITYR 0x0400 >=20 > Maybe GICD_ISENABLER_BASE and GICD_IPRIORITYR_BASE as they are the star= t > of a series of registers? We should keep the naming consistent to both the spec and the Linux heade= rs. > Also what happened to the formatting? Isn't that the usual diff artifact caused by prepending a single character? Which moves the tab stops, also the mailer adding quotation characters? >> + >> +#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) >> * 32) >> +#define GICD_INT_EN_SET_SGI 0x0000ffff >> +#define GICD_INT_DEF_PRI_X4 0xa0a0a0a0 >=20 > This doesn't seem to be used and I'm not sure what GICD_TYPER_IRQS it i= s > trying to achieve. The idea is to calculate the number of implemented SPIs. But I am not a big fan of copying a macro from the emulation code base to the test code. Cheers, Andre. > A comment above and here to make it clear we are talking about offsets > in the distributor and cpu register maps would aid confusion. >=20 >> + >> +#define GICC_CTLR 0x0000 >> +#define GICC_PMR 0x0004 >> + >> +#define GICC_INT_PRI_THRESHOLD 0xf0 >> + >> +#ifndef __ASSEMBLY__ >> + >> +/* >> + * gic_init will try to find all known gics, and then >> + * initialize the gic data for the one found. >> + * returns >> + * 0 : no gic was found >> + * > 0 : the gic version of the gic found >> + */ >> +extern int gic_init(void); >=20 > If we are going to make the library API agnostic I guess returning NULL > or an ops structure would be best here? >=20 >> + >> +#endif /* !__ASSEMBLY__ */ >> +#endif /* _ASMARM_GIC_H_ */ >> diff --git a/lib/arm/gic.c b/lib/arm/gic.c >> new file mode 100644 >> index 000000000000..d655105e058b >> --- /dev/null >> +++ b/lib/arm/gic.c >> @@ -0,0 +1,76 @@ >> +/* >> + * Copyright (C) 2016, Red Hat Inc, Andrew Jones >> + * >> + * This work is licensed under the terms of the GNU LGPL, version 2. >> + */ >> +#include >> +#include >> +#include >> + >> +struct gicv2_data gicv2_data; >> + >> +/* >> + * Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt >> + */ >> +static bool >> +gic_get_dt_bases(const char *compatible, void **base1, void **base2) >> +{ >> + struct dt_pbus_reg reg; >> + struct dt_device gic; >> + struct dt_bus bus; >> + int node, ret; >> + >> + dt_bus_init_defaults(&bus); >> + dt_device_init(&gic, &bus, NULL); >> + >> + node =3D dt_device_find_compatible(&gic, compatible); >> + assert(node >=3D 0 || node =3D=3D -FDT_ERR_NOTFOUND); >> + >> + if (node =3D=3D -FDT_ERR_NOTFOUND) >> + return false; >> + >> + dt_device_bind_node(&gic, node); >> + >> + ret =3D dt_pbus_translate(&gic, 0, ®); >> + assert(ret =3D=3D 0); >> + *base1 =3D ioremap(reg.addr, reg.size); >> + >> + ret =3D dt_pbus_translate(&gic, 1, ®); >> + assert(ret =3D=3D 0); >> + *base2 =3D ioremap(reg.addr, reg.size); >> + >> + return true; >> +} >> + >> +int gicv2_init(void) >> +{ >> + return gic_get_dt_bases("arm,cortex-a15-gic", >> + &gicv2_data.dist_base, &gicv2_data.cpu_base); >> +} >> + >> +int gic_init(void) >> +{ >> + if (gicv2_init()) >> + return 2; >> + return 0; >> +} >> + >> +void gicv2_enable_defaults(void) >> +{ >> + void *dist =3D gicv2_dist_base(); >> + void *cpu_base =3D gicv2_cpu_base(); >> + unsigned int i; >> + >> + gicv2_data.irq_nr =3D GICD_TYPER_IRQS(readl(dist + GICD_TYPER)); >> + if (gicv2_data.irq_nr > 1020) >> + gicv2_data.irq_nr =3D 1020; >> + >> + for (i =3D 0; i < gicv2_data.irq_nr; i +=3D 4) >> + writel(GICD_INT_DEF_PRI_X4, dist + GICD_IPRIORITYR + i); >> + >> + writel(GICD_INT_EN_SET_SGI, dist + GICD_ISENABLER + 0); >> + writel(GICD_ENABLE, dist + GICD_CTLR); >> + >> + writel(GICC_INT_PRI_THRESHOLD, cpu_base + GICC_PMR); >> + writel(GICC_ENABLE, cpu_base + GICC_CTLR); >> +} >> diff --git a/lib/arm64/asm/gic-v2.h b/lib/arm64/asm/gic-v2.h >> new file mode 100644 >> index 000000000000..52226624a209 >> --- /dev/null >> +++ b/lib/arm64/asm/gic-v2.h >> @@ -0,0 +1 @@ >> +#include "../../arm/asm/gic-v2.h" >> diff --git a/lib/arm64/asm/gic.h b/lib/arm64/asm/gic.h >> new file mode 100644 >> index 000000000000..e5eb302a31b4 >> --- /dev/null >> +++ b/lib/arm64/asm/gic.h >> @@ -0,0 +1 @@ >> +#include "../../arm/asm/gic.h" >=20 >=20 > -- > Alex Benn=C3=A9e >=20