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Tue, 09 Nov 2021 08:37:43 -0800 (PST) Message-ID: <2458d27b-75eb-e4f8-c588-efd8c50df5fc@gmail.com> Date: Tue, 9 Nov 2021 13:37:40 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0 Subject: Re: [PATCH 1/2] target/ppc: Fixed call to deferred exception Content-Language: en-US To: "Lucas Mateus Castro (alqotel)" , qemu-devel@nongnu.org, qemu-ppc@nongnu.org References: <20211020125724.78028-1-lucas.araujo@eldorado.org.br> <20211020125724.78028-2-lucas.araujo@eldorado.org.br> From: Daniel Henrique Barboza In-Reply-To: <20211020125724.78028-2-lucas.araujo@eldorado.org.br> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::22e (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-3.364, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Lucas Mateus Castro \(alqotel\)" , richard.henderson@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/20/21 09:57, Lucas Mateus Castro (alqotel) wrote: > From: "Lucas Mateus Castro (alqotel)" > > mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status > after updating the value of FPSCR, but helper_float_check_status > checks fp_status and fp_status isn't updated based on FPSCR and > since the value of fp_status is reset earlier in the instruction, > it's always 0. > > Because of this helper_float_check_status would change the FI bit to 0 > as this bit checks if the last operation was inexact and > float_flag_inexact is always 0. > > These instructions also don't throw exceptions correctly since > helper_float_check_status throw exceptions based on fp_status. > > This commit created a new helper, helper_fpscr_check_status that checks > FPSCR value instead of fp_status and checks for a larger variety of > exceptions than do_float_check_status. > > The hardware used to compare QEMU's behavior to, was a Power9. Extra comma before "was a Power9". Aside from that, LGTM. Thanks, Daniel > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266 > Signed-off-by: Lucas Mateus Castro (alqotel) > --- > target/ppc/fpu_helper.c | 41 ++++++++++++++++++++++++++++++ > target/ppc/helper.h | 1 + > target/ppc/translate/fp-impl.c.inc | 6 ++--- > 3 files changed, 45 insertions(+), 3 deletions(-) > > diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c > index c4896cecc8..f086cb503f 100644 > --- a/target/ppc/fpu_helper.c > +++ b/target/ppc/fpu_helper.c > @@ -414,6 +414,47 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t val, uint32_t nibbles) > ppc_store_fpscr(env, val); > } > > +void helper_fpscr_check_status(CPUPPCState *env) > +{ > + CPUState *cs = env_cpu(env); > + target_ulong fpscr = env->fpscr; > + int error = 0; > + > + if ((fpscr & FP_VXSOFT) && (fpscr_ve != 0)) { > + error = POWERPC_EXCP_FP_VXSOFT; > + } else if ((fpscr & FP_OX) && (fpscr & FP_OE)) { > + error = POWERPC_EXCP_FP_OX; > + } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) { > + error = POWERPC_EXCP_FP_UX; > + } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) { > + error = POWERPC_EXCP_FP_XX; > + } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) { > + error = POWERPC_EXCP_FP_ZX; > + } else if ((fpscr & FP_VXSNAN) && (fpscr_ve != 0)) { > + error = POWERPC_EXCP_FP_VXSNAN; > + } else if ((fpscr & FP_VXISI) && (fpscr_ve != 0)) { > + error = POWERPC_EXCP_FP_VXISI; > + } else if ((fpscr & FP_VXIDI) && (fpscr_ve != 0)) { > + error = POWERPC_EXCP_FP_VXIDI; > + } else if ((fpscr & FP_VXZDZ) && (fpscr_ve != 0)) { > + error = POWERPC_EXCP_FP_VXZDZ; > + } else if ((fpscr & FP_VXIMZ) && (fpscr_ve != 0)) { > + error = POWERPC_EXCP_FP_VXIMZ; > + } else if ((fpscr & FP_VXVC) && (fpscr_ve != 0)) { > + error = POWERPC_EXCP_FP_VXVC; > + } > + > + if (error) { > + cs->exception_index = POWERPC_EXCP_PROGRAM; > + env->error_code = error | POWERPC_EXCP_FP; > + /* Deferred floating-point exception after target FPSCR update */ > + if (fp_exceptions_enabled(env)) { > + raise_exception_err_ra(env, cs->exception_index, > + env->error_code, GETPC()); > + } > + } > +} > + > static void do_float_check_status(CPUPPCState *env, uintptr_t raddr) > { > CPUState *cs = env_cpu(env); > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index 4076aa281e..baa3715e73 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -61,6 +61,7 @@ DEF_HELPER_FLAGS_1(cntlzw32, TCG_CALL_NO_RWG_SE, i32, i32) > DEF_HELPER_FLAGS_2(brinc, TCG_CALL_NO_RWG_SE, tl, tl, tl) > > DEF_HELPER_1(float_check_status, void, env) > +DEF_HELPER_1(fpscr_check_status, void, env) > DEF_HELPER_1(reset_fpstatus, void, env) > DEF_HELPER_2(compute_fprf_float64, void, env, i64) > DEF_HELPER_3(store_fpscr, void, env, i64, i32) > diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc > index 9f7868ee28..0a9b1ecc60 100644 > --- a/target/ppc/translate/fp-impl.c.inc > +++ b/target/ppc/translate/fp-impl.c.inc > @@ -782,7 +782,7 @@ static void gen_mtfsb1(DisasContext *ctx) > tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); > } > /* We can raise a deferred exception */ > - gen_helper_float_check_status(cpu_env); > + gen_helper_fpscr_check_status(cpu_env); > } > > /* mtfsf */ > @@ -818,7 +818,7 @@ static void gen_mtfsf(DisasContext *ctx) > tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); > } > /* We can raise a deferred exception */ > - gen_helper_float_check_status(cpu_env); > + gen_helper_fpscr_check_status(cpu_env); > tcg_temp_free_i64(t1); > } > > @@ -851,7 +851,7 @@ static void gen_mtfsfi(DisasContext *ctx) > tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); > } > /* We can raise a deferred exception */ > - gen_helper_float_check_status(cpu_env); > + gen_helper_fpscr_check_status(cpu_env); > } > > /*** Floating-point load ***/ >