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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7326ace1270sm897278b3a.114.2025.02.15.10.42.25 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 15 Feb 2025 10:42:25 -0800 (PST) Message-ID: <24b0147e-6825-4daa-afcd-a493685f9f6b@linaro.org> Date: Sat, 15 Feb 2025 10:42:23 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] target/rx: Remove TCG_CALL_NO_WG from helpers which write env From: Richard Henderson To: qemu-devel@nongnu.org References: <20250215021654.1786679-1-keithp@keithp.com> <20250215021654.1786679-6-keithp@keithp.com> <87jz9r1s3h.fsf@keithp.com> <21d559fc-1d81-4725-9523-60949a41e5a7@linaro.org> Content-Language: en-US In-Reply-To: <21d559fc-1d81-4725-9523-60949a41e5a7@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/15/25 09:09, Richard Henderson wrote: > On 2/15/25 01:21, Keith Packard via wrote: >> >>> Functions which modify virtual machine state (such as virtual >>> registers stored in memory) must not be marked TCG_CALL_NO_WG as that >>> tells the optimizer that virtual registers values already loaded in >>> machine registers are still valid, hence discards any changes which >>> these helpers may have made. >> >> I still don't understand the restrictions on using these flags. I just >> had to disable this flag for other helpers which only set conditions >> codes in PSW and FPSW. Is that expected? When are these flags supposed >> to be valid? > > Yes, that's expected. > > The state of affairs is not helped by the rx target's misuse of tcg globals. > > A target should define tcg globals for values that are used frequently for emulation.  The > bits of the PSW certainly fit that bill, because they're touched by most arithmetic > operations. > > However, fpsw, bpsw, bpc, isp, fintv, and intb are only used in move_to/from_cr and RTFI. > This is infrequent, so simply loading and storing to env is preferred.  E.g. > >     tcg_gen_ld_i32(value, tcg_env, offsetof(CPURXState, fpsw)); > To finish my thought here, > +DEF_HELPER_2(set_psw_rte, void, env, i32) > +DEF_HELPER_2(set_psw, void, env, i32) > +DEF_HELPER_1(scmpu, void, env) > +DEF_HELPER_2(swhile, void, env, i32) > +DEF_HELPER_2(suntil, void, env, i32) > +DEF_HELPER_2(rmpa, void, env, i32) are absolutely correct, in that they modify all of the psw_* globals. > +DEF_HELPER_2(racw, void, env, i32) is currently correct, in that it modifies cpu_acc. That said, there's no reason that function could not be expanded inline: tcg_gen_shli_i64(cpu_acc, cpu_acc, imm); tcg_gen_addi_i64(cpu_acc, cpu_acc, 0x0000000080000000ull); tcg_gen_smin_i64(cpu_acc, cpu_acc, tcg_constant_i64(0x00007fff00000000ull)); tcg_gen_smax_i64(cpu_acc, cpu_acc, tcg_constant_i64(0xffff800000000000ull)); tcg_gen_andi_i64(cpu_acc, cpu_acc, 0xffffffff00000000ull); r~