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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id r7sm7712950wma.39.2022.01.30.15.35.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 30 Jan 2022 15:35:55 -0800 (PST) Message-ID: <24f93c21-33a6-091f-206f-b80f505b6ddb@amsat.org> Date: Mon, 31 Jan 2022 00:35:54 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v1 5/6] hw/misc: Add a model of the Xilinx ZynqMP APU Control Content-Language: en-US To: "Edgar E. Iglesias" , qemu-devel@nongnu.org Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org References: <20220130231206.34035-1-edgar.iglesias@gmail.com> <20220130231206.34035-6-edgar.iglesias@gmail.com> In-Reply-To: <20220130231206.34035-6-edgar.iglesias@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= via On 31/1/22 00:12, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Add a model of the Xilinx ZynqMP APU Control. > > Signed-off-by: Edgar E. Iglesias > --- > include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 91 +++++++++ > hw/misc/xlnx-zynqmp-apu-ctrl.c | 257 +++++++++++++++++++++++++ > hw/misc/meson.build | 1 + > 3 files changed, 349 insertions(+) > create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h > create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c > > diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h > new file mode 100644 > index 0000000000..44bf264cef > --- /dev/null > +++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h > @@ -0,0 +1,91 @@ > +/* > + * QEMU model of ZynqMP APU Control. > + * > + * Copyright (c) 2013-2022 Xilinx Inc > + * SPDX-License-Identifier: GPL-2.0-or-later > + * > + * Written by Peter Crosthwaite and > + * Edgar E. Iglesias > + * > + */ > + > +#include "hw/sysbus.h" > +#include "hw/register.h" > +#include "target/arm/cpu.h" > + > +#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl" > + > +#define XLNX_ZYNQMP_APU(obj) \ > + OBJECT_CHECK(XlnxZynqMPAPUCtrl, (obj), TYPE_XLNX_ZYNQMP_APU_CTRL) ... > +#define APU_R_MAX ((R_PWRSTAT) + 1) > + > +#define NUM_CPUS 4 Hmm isn't it APU_MAX_CPU? > +typedef struct XlnxZynqMPAPUCtrl { > + SysBusDevice busdev; > + > + ARMCPU *cpus[NUM_CPUS]; > + /* WFIs towards PMU. */ > + qemu_irq wfi_out[4]; > + /* CPU Power status towards INTC Redirect. */ > + qemu_irq cpu_power_status[4]; > + qemu_irq irq_imr; > + > + uint8_t cpu_pwrdwn_req; > + uint8_t cpu_in_wfi; > + > + RegisterInfoArray *reg_array; > + uint32_t regs[APU_R_MAX]; > + RegisterInfo regs_info[APU_R_MAX]; > +} XlnxZynqMPAPUCtrl;