From: Thomas Huth <thuth@redhat.com>
To: David Hildenbrand <david@redhat.com>, qemu-devel@nongnu.org
Cc: rth@twiddle.net, agraf@suse.de, Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG
Date: Wed, 28 Jun 2017 16:21:20 +0200 [thread overview]
Message-ID: <251b8047-7df4-50a5-cce7-b66858c781a1@redhat.com> (raw)
In-Reply-To: <20170627161032.5014-1-david@redhat.com>
On 27.06.2017 18:10, David Hildenbrand wrote:
> STFL bit 4 and 5 are just indications to the guest, which TLB entries an
> IDTE call will clear. These are performance indicators for the guest.
>
> STFL bit 4:
> INVALIDATE DAT TABLE ENTRY (IDTE) performs
> the invalidation-and-clearing operation by
> selectively clearing TLB segment-table entries
> when a segment-table entry or entries are
> invalidated. IDTE also performs the clearing-by-
> ASCE operation. Unless bit 4 is one, IDTE simply
> purges all TLBs. Bit 3 is one if bit 4 is one.
>
> We can simply set STFL bit 4 ("idtes") and still purge the complete TLB.
> Purging more than advertised is never bad. E.g. Linux doesn't even care
> about this bit. We can optimized this later.
Not sure, but why do we need this bit in add_qemu_cpu_model_features()
if Linux does not care about it? We will get it automatically once we
support the z9 in TCG...
Thomas
next prev parent reply other threads:[~2017-06-28 14:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-27 16:10 [Qemu-devel] [PATCH v1] s390x/cpumodel: allow to enable "idtes" feature for TCG David Hildenbrand
2017-06-28 14:21 ` Thomas Huth [this message]
2017-06-28 17:02 ` David Hildenbrand
2017-06-29 7:05 ` Thomas Huth
2017-06-30 19:22 ` Richard Henderson
2017-07-03 11:07 ` Thomas Huth
2017-07-03 11:38 ` David Hildenbrand
2017-07-03 16:08 ` Richard Henderson
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