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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.gmail.com with ESMTPSA id se22sm4035525ejb.32.2021.09.06.07.29.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 06 Sep 2021 07:29:54 -0700 (PDT) Subject: Re: [PATCH] target/i386: add missing bits to CR4_RESERVED_MASK To: "Richard W.M. Jones" , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= References: <20210831175033.175584-1-berrange@redhat.com> <20210831175740.GZ26415@redhat.com> From: Paolo Bonzini Message-ID: <256b12ed-dfb9-8b18-05e3-f39dbf45f6e1@redhat.com> Date: Mon, 6 Sep 2021 16:29:49 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210831175740.GZ26415@redhat.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=pbonzini@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=216.205.24.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -54 X-Spam_score: -5.5 X-Spam_bar: ----- X-Spam_report: (-5.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.391, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.332, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lara Lazier , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 31/08/21 19:57, Richard W.M. Jones wrote: >> diff --git a/target/i386/cpu.h b/target/i386/cpu.h >> index 6c50d3ab4f..ce85f1a29d 100644 >> --- a/target/i386/cpu.h >> +++ b/target/i386/cpu.h >> @@ -257,6 +257,7 @@ typedef enum X86Seg { >> | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \ >> | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \ >> | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK |CR4_UMIP_MASK \ >> + | CR4_LA57_MASK | CR4_VMXE_MASK | CR4_SMXE_MASK \ >> | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \ >> | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK)) > First thing to say is I tested this locally and it fixes the > problem seen inhttps://bugzilla.redhat.com/show_bug.cgi?id=1999700. > I will also add this patch to Fedora soon. So: > > Tested-by: Richard W.M. Jones > > But my question is, does this mean that every time a new CPU feature > appears we must remember to update this code? This is used only by TCG, which explains why VMXE/SMXE were not there; however, LA57 is missing indeed. New features must be included both here and in cr4_reserved_bits, but only if TCG supports them, otherwise they can be left out. Since VMXE/SMXE are not supported by TCG, they should be either added both here and in cr4_reserved_bits (keyed on env->features[FEAT_1_ECX] & CPUID_EXT_{VMX,SMX} respectively), or they should not be added to CR4_RESERVED_MASK either. On the other hand LA57 is already handled by cr4_reserved_bits, so it is okay to just add it here. Thanks, Paolo