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From: Richard Henderson <rth@twiddle.net>
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Date: Mon, 26 Sep 2016 14:41:11 -0700
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Subject: Re: [Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions
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To: Sagar Karandikar <sagark@eecs.berkeley.edu>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, kbastian@mail.uni-paderborn.de

On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
> +void helper_fence_i(CPURISCVState *env)
> +{
> +    RISCVCPU *cpu = riscv_env_get_cpu(env);
> +    CPUState *cs = CPU(cpu);
> +    /* Flush QEMU's TLB */
> +    tlb_flush(cs, 1);
> +    /* ARM port seems to not know if this is okay inside a TB
> +       But we need to do it */
> +    tb_flush(cs);
> +}

You should not need to tb_flush for fence_i.  QEMU's internals auto-detect when 
a memory write invalidates a TB.


r~