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From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au
Subject: Re: [PATCH v2 4/5] target/ppc: keep ins_cnt/cyc_cnt cleared if MMCR0_FC is set
Date: Mon, 3 Jan 2022 18:50:09 -0300	[thread overview]
Message-ID: <25b90f46-befa-3fc9-cdef-e6e999765f33@gmail.com> (raw)
In-Reply-To: <0b9b2a07-4b0c-4095-9365-d95139e182fc@linaro.org>



On 1/3/22 18:38, Richard Henderson wrote:
> On 1/3/22 10:53 AM, Daniel Henrique Barboza wrote:
>> pmu_update_summaries() is not considering the case where the PMU can be
>> turned off (i.e. stop counting all events) if MMCR0_FC is set,
>> regardless of the other frozen counter bits state. This use case was
>> covered in the late pmc_get_event(), via the also gone pmc_is_inactive(),
>> that would return an invalid event if MMCR0_FC was set.
>>
>> This use case is exercised by the back_to_back_ebbs_test Linux kernel
>> selftests [1]. As it is today, after enabling EBB exceptions, the test
>> will report an additional event-based branch being taken and will fail.
>> Other tests, such as cycles_test.c, will report additional cycles being
>> calculated in the counters because we're not freezing the PMU quick
>> enough.
>>
>> Fix pmu_update_summaries() by keeping env->ins_cnt and env->cyc_cnt
>> cleared when MMCR0_FC is set.
>>
>> [1] tools/testing/selftests/powerpc/pmu/ebb/back_to_back_ebbs_test.c
>>
>> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
>> ---
>>   target/ppc/power8-pmu.c | 5 +++++
>>   1 file changed, 5 insertions(+)
>>
>> diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
>> index 7fc7d91109..73713ca2a3 100644
>> --- a/target/ppc/power8-pmu.c
>> +++ b/target/ppc/power8-pmu.c
>> @@ -40,6 +40,10 @@ void pmu_update_summaries(CPUPPCState *env)
>>       int ins_cnt = 0;
>>       int cyc_cnt = 0;
>> +    if (mmcr0 & MMCR0_FC) {
>> +        goto hflags_calc;
>> +    }
>> +
>>       if (!(mmcr0 & MMCR0_FC14) && mmcr1 != 0) {
>>           target_ulong sel;
>> @@ -71,6 +75,7 @@ void pmu_update_summaries(CPUPPCState *env)
>>       ins_cnt |= !(mmcr0 & MMCR0_FC56) << 5;
>>       cyc_cnt |= !(mmcr0 & MMCR0_FC56) << 6;
>> + hflags_calc:
> 
> Good catch, but should be folded into patch 1 to avoid bisection breakage.

Fair point. Given that you have a suggestion in patch 5 as well I'll send a v3.


Thanks,


Daniel



> 
> 
> r~


  reply	other threads:[~2022-01-03 21:51 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-03 18:53 [PATCH v2 0/5] Reorg ppc64 pmu insn counting Daniel Henrique Barboza
2022-01-03 18:53 ` [PATCH v2 1/5] target/ppc: Cache per-pmc insn and cycle count settings Daniel Henrique Barboza
2022-01-03 21:26   ` Richard Henderson
2022-01-03 18:53 ` [PATCH v2 2/5] target/ppc: Rewrite pmu_increment_insns Daniel Henrique Barboza
2022-01-03 18:53 ` [PATCH v2 3/5] target/ppc: Use env->pnc_cyc_cnt Daniel Henrique Barboza
2022-01-03 18:53 ` [PATCH v2 4/5] target/ppc: keep ins_cnt/cyc_cnt cleared if MMCR0_FC is set Daniel Henrique Barboza
2022-01-03 21:38   ` Richard Henderson
2022-01-03 21:50     ` Daniel Henrique Barboza [this message]
2022-01-03 18:53 ` [PATCH v2 5/5] target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0() Daniel Henrique Barboza
2022-01-03 21:40   ` Richard Henderson

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