[Qemu-devel] [PATCH 0/4] Misc MIPS fixes and improvements for October 2018

[Qemu-devel] [PATCH 0/4] Misc MIPS fixes and improvements for October 2018

[Aleksandar Markovic]

From: Aleksandar Markovic <amarkovic@wavecomp.com>

This series contains support for DSP R3 availability control and
emulation of nanoMIPS EVA instructions.

Dimitrije Nikolic (2):
  target/mips: Add opcodes for nanoMIPS EVA instructions
  target/mips: Implement emulation of nanoMIPS EVA instructions

Stefan Markovic (2):
  target/mips: Add bit definitions for DSP R3 ASE
  target/mips: Add availability control for DSP R3 ASE

 target/mips/cpu.h                |   1 +
 target/mips/internal.h           |  11 ++--
 target/mips/mips-defs.h          |   1 +
 target/mips/translate.c          | 108 ++++++++++++++++++++++++++++++++++++++-
 target/mips/translate_init.inc.c |   3 +-
 5 files changed, 119 insertions(+), 5 deletions(-)

-- 
2.7.4

[Qemu-devel] [PATCH 1/4] target/mips: Add bit definitions for DSP R3 ASE

[Aleksandar Markovic]

From: Stefan Markovic <smarkovic@wavecomp.com>

Add DSP R3 ASE related bit definition for insn_flags and hflags.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/cpu.h       | 1 +
 target/mips/mips-defs.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 28af4d1..4160699 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -598,6 +598,7 @@ struct CPUMIPSState {
     /* MIPS DSP resources access. */
 #define MIPS_HFLAG_DSP   0x080000  /* Enable access to MIPS DSP resources. */
 #define MIPS_HFLAG_DSPR2 0x100000  /* Enable access to MIPS DSPR2 resources. */
+#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resources.*/
     /* Extra flag about HWREna register. */
 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
 #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index c8e9979..b27b7ae 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -47,6 +47,7 @@
 #define   ASE_MDMX      0x00040000
 #define   ASE_DSP       0x00080000
 #define   ASE_DSPR2     0x00100000
+#define   ASE_DSPR3     0x02000000
 #define   ASE_MT        0x00200000
 #define   ASE_SMARTMIPS 0x00400000
 #define   ASE_MICROMIPS 0x00800000
-- 
2.7.4

Re: [Qemu-devel] [PATCH 1/4] target/mips: Add bit definitions for DSP R3 ASE

[Philippe Mathieu-Daudé]

Hi Aleksandar and Stefan,

On 04/10/2018 14:34, Aleksandar Markovic wrote:
> From: Stefan Markovic <smarkovic@wavecomp.com>
> 
> Add DSP R3 ASE related bit definition for insn_flags and hflags.
> 
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
>  target/mips/cpu.h       | 1 +
>  target/mips/mips-defs.h | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 28af4d1..4160699 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -598,6 +598,7 @@ struct CPUMIPSState {
>      /* MIPS DSP resources access. */
>  #define MIPS_HFLAG_DSP   0x080000  /* Enable access to MIPS DSP resources. */
>  #define MIPS_HFLAG_DSPR2 0x100000  /* Enable access to MIPS DSPR2 resources. */
> +#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resources.*/

I find it confusing to add this in the middle (rather that at the end)
of this list. It looks also bug prone, if someone add another definition
at the end of the list he might use the same value.

>      /* Extra flag about HWREna register. */
>  #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
>  #define MIPS_HFLAG_SBRI  0x400000 /* R6 SDBBP causes RI excpt. in user mode */
> diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
> index c8e9979..b27b7ae 100644
> --- a/target/mips/mips-defs.h
> +++ b/target/mips/mips-defs.h
> @@ -47,6 +47,7 @@
>  #define   ASE_MDMX      0x00040000
>  #define   ASE_DSP       0x00080000
>  #define   ASE_DSPR2     0x00100000
> +#define   ASE_DSPR3     0x02000000

Ditto.

>  #define   ASE_MT        0x00200000
>  #define   ASE_SMARTMIPS 0x00400000
>  #define   ASE_MICROMIPS 0x00800000

What about adding this patch on top of the "mips: Clean the 'insn_flags'
namespace" patch which use your suggestion and let available space for
this ASE flag?

https://lists.gnu.org/archive/html/qemu-devel/2018-09/msg04070.html

Thanks,

Phil.

[Qemu-devel] [PATCH 2/4] target/mips: Add availability control for DSP R3 ASE

[Aleksandar Markovic]

From: Stefan Markovic <smarkovic@wavecomp.com>

Add infrastructure for availability control for DSP R3 ASE MIPS
instructions. Only BPOSGE32C currently belongs to DSP R3 ASE, but
this is likely to be changed in near future.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/internal.h           | 11 ++++++++---
 target/mips/translate.c          | 13 ++++++++++++-
 target/mips/translate_init.inc.c |  3 ++-
 3 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index e41051f..3c5867e 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -307,8 +307,8 @@ static inline void compute_hflags(CPUMIPSState *env)
     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
                      MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
-                     MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
-                     MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
+                     MIPS_HFLAG_DSPR3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
+                     MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
     if (env->CP0_Status & (1 << CP0St_ERL)) {
         env->hflags |= MIPS_HFLAG_ERL;
     }
@@ -355,7 +355,12 @@ static inline void compute_hflags(CPUMIPSState *env)
         (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
         env->hflags |= MIPS_HFLAG_SBRI;
     }
-    if (env->insn_flags & ASE_DSPR2) {
+    if (env->insn_flags & ASE_DSPR3) {
+        if (env->CP0_Status & (1 << CP0St_MX)) {
+            env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
+                           MIPS_HFLAG_DSPR3;
+        }
+    } else if (env->insn_flags & ASE_DSPR2) {
         /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
            so enable to access DSPR2 resources. */
         if (env->CP0_Status & (1 << CP0St_MX)) {
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab16cdb..d64a1da 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1868,6 +1868,17 @@ static inline void check_dspr2(DisasContext *ctx)
     }
 }
 
+static inline void check_dspr3(DisasContext *ctx)
+{
+    if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR3))) {
+        if (ctx->insn_flags & ASE_DSP) {
+            generate_exception_end(ctx, EXCP_DSPDIS);
+        } else {
+            generate_exception_end(ctx, EXCP_RI);
+        }
+    }
+}
+
 /* This code generates a "reserved instruction" exception if the
    CPU does not support the instruction set corresponding to flags. */
 static inline void check_insn(DisasContext *ctx, int flags)
@@ -20098,7 +20109,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
                     break;
                 case NM_BPOSGE32C:
-                    check_dspr2(ctx);
+                    check_dspr3(ctx);
                     {
                         int32_t imm = extract32(ctx->opcode, 1, 13) |
                                       extract32(ctx->opcode, 0, 1) << 13;
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index b3320b9..d7cd4ee 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -485,7 +485,8 @@ const mips_def_t mips_defs[] =
         .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
         .SEGBITS = 32,
         .PABITS = 32,
-        .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_MT,
+        .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 |
+                      ASE_MT,
         .mmu_type = MMU_TYPE_R4000,
     },
 #if defined(TARGET_MIPS64)
-- 
2.7.4

[Qemu-devel] [PATCH 3/4] target/mips: Add opcodes for nanoMIPS EVA instructions

[Aleksandar Markovic]

From: Dimitrije Nikolic <dnikolic@wavecomp.com>

Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index d64a1da..b0b2f40 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16499,6 +16499,22 @@ enum {
     NM_P_SC      = 0x0b,
 };
 
+/* P.LS.E0 instruction pool */
+enum {
+    NM_LBE      = 0x00,
+    NM_SBE      = 0x01,
+    NM_LBUE     = 0x02,
+    NM_P_PREFE  = 0x03,
+    NM_LHE      = 0x04,
+    NM_SHE      = 0x05,
+    NM_LHUE     = 0x06,
+    NM_CACHEE   = 0x07,
+    NM_LWE      = 0x08,
+    NM_SWE      = 0x09,
+    NM_P_LLE    = 0x0a,
+    NM_P_SCE    = 0x0b,
+};
+
 /* P.LS.WM instruction pool */
 enum {
     NM_LWM       = 0x00,
-- 
2.7.4

[Qemu-devel] [PATCH 4/4] target/mips: Implement emulation of nanoMIPS EVA instructions

[Aleksandar Markovic]

From: Dimitrije Nikolic <dnikolic@wavecomp.com>

Implement emulation of nanoMIPS EVA instructions. They are all
part of P.LS.E0 instruction pool, or one of its subpools.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index b0b2f40..3adf31f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1979,6 +1979,17 @@ static inline void check_nms(DisasContext *ctx)
     }
 }
 
+/*
+ * This code generates a "reserved instruction" exception if the
+ * Config5 EVA bit is NOT set.
+ */
+static inline void check_eva(DisasContext *ctx)
+{
+    if (!unlikely(ctx->CP0_Config5 & (1 << CP0C5_EVA))) {
+        generate_exception_end(ctx, EXCP_RI);
+    }
+}
+
 
 /* Define small wrappers for gen_load_fpr* so that we have a uniform
    calling interface for 32 and 64-bit FPRs.  No sense in changing
@@ -20011,6 +20022,74 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
                     break;
                 }
                 break;
+            case NM_P_LS_E0:
+                check_eva(ctx);
+                switch (extract32(ctx->opcode, 11, 4)) {
+                case NM_LBE:
+                    gen_ld(ctx, OPC_LBE, rt, rs, s);
+                    break;
+                case NM_SBE:
+                    gen_st(ctx, OPC_SBE, rt, rs, s);
+                    break;
+                case NM_LBUE:
+                    gen_ld(ctx, OPC_LBUE, rt, rs, s);
+                    break;
+                case NM_P_PREFE:
+                    if (rt == 31) {
+                        /* SYNCIE */
+                        /* Break the TB to be able to sync copied instructions
+                           immediately */
+                        ctx->base.is_jmp = DISAS_STOP;
+                    } else {
+                        /* PREF */
+                        /* Treat as NOP. */
+                    }
+                    break;
+                case NM_LHE:
+                    gen_ld(ctx, OPC_LHE, rt, rs, s);
+                    break;
+                case NM_SHE:
+                    gen_st(ctx, OPC_SHE, rt, rs, s);
+                    break;
+                case NM_LHUE:
+                    gen_ld(ctx, OPC_LHUE, rt, rs, s);
+                    break;
+                case NM_CACHEE:
+                    /* Treat as no-op */
+                    if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) {
+                        gen_cache_operation(ctx, rt, rs, s);
+                    }
+                    break;
+                case NM_LWE:
+                    gen_ld(ctx, OPC_LWE, rt, rs, s);
+                    break;
+                case NM_SWE:
+                    gen_st(ctx, OPC_SWE, rt, rs, s);
+                    break;
+                case NM_P_LLE:
+                    switch (extract32(ctx->opcode, 2, 2)) {
+                    case NM_LL:
+                        gen_ld(ctx, OPC_LLE, rt, rs, s);
+                        break;
+                    case NM_LLWP:
+                    default:
+                        generate_exception_end(ctx, EXCP_RI);
+                        break;
+                    }
+                    break;
+                case NM_P_SCE:
+                    switch (extract32(ctx->opcode, 2, 2)) {
+                    case NM_SC:
+                        gen_st_cond(ctx, OPC_SCE, rt, rs, s);
+                        break;
+                    case NM_SCWP:
+                    default:
+                        generate_exception_end(ctx, EXCP_RI);
+                        break;
+                    }
+                    break;
+                }
+                break;
             case NM_P_LS_WM:
             case NM_P_LS_UAWM:
                 check_nms(ctx);
-- 
2.7.4

Re: [Qemu-devel] [PATCH 0/4] Misc MIPS fixes and improvements for October 2018

[Philippe Mathieu-Daudé]

Hi Aleksandar,

On 04/10/2018 14:34, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
> 
> This series contains support for DSP R3 availability control and
> emulation of nanoMIPS EVA instructions.
> 
> Dimitrije Nikolic (2):
>   target/mips: Add opcodes for nanoMIPS EVA instructions
>   target/mips: Implement emulation of nanoMIPS EVA instructions
> 
> Stefan Markovic (2):
>   target/mips: Add bit definitions for DSP R3 ASE
>   target/mips: Add availability control for DSP R3 ASE

It seems all these patches miss their author Signed-off-by tag.

Regards,

Phil.