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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429952e2e06sm15436900f8f.46.2025.10.27.10.38.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Oct 2025 10:38:10 -0700 (PDT) Message-ID: <25d22f06-69e2-4954-9bd9-f73f899fc114@redhat.com> Date: Mon, 27 Oct 2025 18:38:08 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 22/27] hw/arm/smmuv3-accel: Add support for ATS Content-Language: en-US To: Nicolin Chen Cc: Shameer Kolothum , qemu-arm@nongnu.org, qemu-devel@nongnu.org, peter.maydell@linaro.org, jgg@nvidia.com, ddutile@redhat.com, berrange@redhat.com, nathanc@nvidia.com, mochs@nvidia.com, smostafa@google.com, wangzhou1@hisilicon.com, jiangkunkun@huawei.com, jonathan.cameron@huawei.com, zhangfei.gao@linaro.org, zhenzhong.duan@intel.com, yi.l.liu@intel.com, shameerkolothum@gmail.com References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-23-skolothumtho@nvidia.com> <26f4d9b2-75be-4913-bb60-01e647a7ec83@redhat.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/27/25 6:13 PM, Nicolin Chen wrote: > Hi Eric, > > On Mon, Oct 27, 2025 at 05:59:13PM +0100, Eric Auger wrote: >> On 9/29/25 3:36 PM, Shameer Kolothum wrote: >>> QEMU SMMUv3 does not enable ATS (Address Translation Services) by default. >>> When accelerated mode is enabled and the host SMMUv3 supports ATS, it can >>> be useful to report ATS capability to the guest so it can take advantage >>> of it if the device also supports ATS. >>> >>> Note: ATS support cannot be reliably detected from the host SMMUv3 IDR >>> registers alone, as firmware ACPI IORT tables may override them. The >>> user must therefore ensure the support before enabling it. >> This looks incomplete to me. ATS is a big topic in itself. I would >> prefer we do not advertise it until we do not have full support for it >> (including emulation). Comparing to >> c049bf5bb9dd ("intel_iommu: Add support for ATS") which was recently >> contributed we miss at least translation request implementations >> (PCIIOMMUOps ats_request_translation callback implementation). >> >> See: >> https://lore.kernel.org/all/20250628180226.133285-11-clement.mathieu--drif@eviden.com/#r > In accelerated SMMUv3 case, ATS translation and invalidation are > done by the physical SMMU. Wondering why do we need this? in 06/27 you still can have emulated EPs hotplugged in the loop, no? I remember some discussions with Peter who was also reluctant in general to introduce some partial feature support. I think in general this is a good policy to have features emulated and then accelerated. That's also good for testing in case we can bring up some test env. Thanks Eric > > IIRC, intel is mixing their emulated translation and accelerated > one, and their pasid table is not integrated like SMMU's CD table > that we already passed entirely via the STE. > >> Also in SMMU spec I see other stuff like STE.EATS, ATS skipping stage 1, >> ... Here I only see  SMMU_CMD_ATC_INV and this is only implemented for >> accel. I think I would rather stick to the minimum in this series, ie. >> reject in case of ATS mismatch (for testing purpose you will just need a >> small hack until we get ATS support), work on ATS enablement in parallel > That SMMU_CMD_ATC_INV seems to be the only thing we need for ATS.. > > Thanks > Nicolin >