From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Ilya Leoshkevich <iii@linux.ibm.com>,
Peter Maydell <peter.maydell@linaro.org>,
Alistair Francis <alistair23@gmail.com>
Cc: qemu-devel@nongnu.org, Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL v2 00/47] riscv-to-apply queue
Date: Mon, 30 Sep 2024 20:04:38 -0300 [thread overview]
Message-ID: <25d74ba0-d13a-4a13-be03-d57f53dd1bce@ventanamicro.com> (raw)
In-Reply-To: <4e3ab59f55937b846fc214f3c3ca3e15c4afb19c.camel@linux.ibm.com>
On 9/30/24 9:10 AM, Ilya Leoshkevich wrote:
> On Sat, 2024-09-28 at 17:40 -0300, Daniel Henrique Barboza wrote:
>>
>>
>> On 9/28/24 8:34 AM, Peter Maydell wrote:
>>> On Tue, 24 Sept 2024 at 23:18, Alistair Francis
>>> <alistair23@gmail.com> wrote:
>>>>
>>>> The following changes since commit
>>>> 01dc65a3bc262ab1bec8fe89775e9bbfa627becb:
>>>>
>>>> Merge tag 'pull-target-arm-20240919' of
>>>> https://git.linaro.org/people/pmaydell/qemu-arm into staging
>>>> (2024-09-19 14:15:15 +0100)
>>>>
>>>> are available in the Git repository at:
>>>>
>>>> https://github.com/alistair23/qemu.git tags/pull-riscv-to-
>>>> apply-20240925-1
>>>>
>>>> for you to fetch changes up to
>>>> 6bfa92c5757fe7a9580e1f6e065076777cae650f:
>>>>
>>>> bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML
>>>> Files (2024-09-24 12:53:16 +1000)
>>>>
>>>> ----------------------------------------------------------------
>>>> RISC-V PR for 9.2
>>>>
>>>> * Add a property to set vl to ceil(AVL/2)
>>>> * Enable numamem testing for RISC-V
>>>> * Consider MISA bit choice in implied rule
>>>> * Fix the za64rs priv spec requirements
>>>> * Enable Bit Manip for OpenTitan Ibex CPU
>>>> * Fix the group bit setting of AIA with KVM
>>>> * Stop timer with infinite timecmp
>>>> * Add 'fcsr' register to QEMU log as a part of F extension
>>>> * Fix riscv64 build on musl libc
>>>> * Add preliminary textra trigger CSR functions
>>>> * RISC-V IOMMU support
>>>> * RISC-V bsd-user support
>>>> * Respect firmware ELF entry point
>>>> * Add Svvptc extension support
>>>> * Fix masking of rv32 physical address
>>>> * Fix linking problem with semihosting disabled
>>>> * Fix IMSIC interrupt state updates
>>>>
>>>
>>> This fails the riscv qos-tests on s390x. My guess is that the new
>>> IOMMU support has endianness bugs and fails on bigendian hosts.
>>>
>>> https://gitlab.com/qemu-project/qemu/-/jobs/7942189143
>>>
>>> full test log (4MB) at
>>> https://qemu-project.gitlab.io/-/qemu/-/jobs/7942189143/artifacts/build/meson-logs/testlog.txt
>>>
>>> The assertion failure is
>>> ERROR:../tests/qtest/riscv-iommu-test.c:72:test_reg_reset:
>>> assertion
>>> failed (cap & RISCV_IOMMU_CAP_VERSION == 0x10): (0 == 16)
>>
>> The root cause is that the qtests I added aren't considering the
>> endianess of the
>> host. The RISC-V IOMMU is being implemented as LE only and all regs
>> are being
>> read/written in memory as LE. The qtest read/write helpers must take
>> the qtest
>> endianess into account. We make this type of handling in other qtest
>> archs like
>> ppc64.
>>
>> I have a fix for the tests but I'm unable to run the ubuntu-22.04-
>> s390x-all-system
>> job to verify it, even after setting Cirrus like Thomas taught me a
>> week ago. In
>> fact I have no 'ubuntu-22-*' jobs available to run.
>>
>> If there's a way to run these ubuntu s390x tests, let me know.
>> Otherwise I'm inclined
>> to remove the IOMMU qtests for now until I'm able to verify that
>> they'll work in a
>> BE host (I'll install a BE VM to verify).
>
> You can get a free s390x VM here:
>
> https://linuxone.cloud.marist.edu/#/register?flag=VM
Thanks! This was surprisingly easy to set up and run. Please send my best regards
to the LinuxOne Community Cloud team.
Peter, in fact there were some endianness problems in the code like you hinted
before. I fixed them up and the tests are now (apparently) passing. I'll clean
stuff up and see if I can send a new version of the whole series in the next
few days.
Thanks,
Daniel
>
> Best regards,
> Ilya
>
> [...]
prev parent reply other threads:[~2024-09-30 23:05 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-24 22:17 [PULL v2 00/47] riscv-to-apply queue Alistair Francis
2024-09-24 22:17 ` [PULL v2 01/47] target/riscv: Add a property to set vl to ceil(AVL/2) Alistair Francis
2024-09-24 22:17 ` [PULL v2 02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V Alistair Francis
2024-09-24 22:17 ` [PULL v2 03/47] tests/qtest/bios-tables-test.c: Enable numamem testing " Alistair Francis
2024-09-24 22:17 ` [PULL v2 04/47] tests/acpi: Add expected ACPI SRAT AML file " Alistair Francis
2024-09-24 22:17 ` [PULL v2 05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule Alistair Francis
2024-09-24 22:17 ` [PULL v2 06/47] target/riscv: fix za64rs enabling Alistair Francis
2024-09-24 22:17 ` [PULL v2 07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU Alistair Francis
2024-09-24 22:17 ` [PULL v2 08/47] target/riscv/kvm: Fix the group bit setting of AIA Alistair Francis
2024-09-24 22:17 ` [PULL v2 09/47] target/riscv: Stop timer with infinite timecmp Alistair Francis
2024-09-24 22:17 ` [PULL v2 10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension Alistair Francis
2024-09-24 22:17 ` [PULL v2 11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc Alistair Francis
2024-09-24 22:17 ` [PULL v2 12/47] target/riscv: Preliminary textra trigger CSR writting support Alistair Francis
2024-09-24 22:17 ` [PULL v2 13/47] target/riscv: Add textra matching condition for the triggers Alistair Francis
2024-09-24 22:17 ` [PULL v2 14/47] exec/memtxattr: add process identifier to the transaction attributes Alistair Francis
2024-09-24 22:17 ` [PULL v2 15/47] hw/riscv: add riscv-iommu-bits.h Alistair Francis
2024-09-24 22:17 ` [PULL v2 16/47] hw/riscv: add RISC-V IOMMU base emulation Alistair Francis
2024-09-28 20:22 ` Peter Maydell
2024-09-28 21:01 ` Daniel Henrique Barboza
2024-09-29 15:46 ` Peter Maydell
2024-10-01 22:14 ` Tomasz Jeznach
2024-10-01 23:00 ` Daniel Henrique Barboza
2024-10-01 23:19 ` Tomasz Jeznach
2024-10-01 22:24 ` Tomasz Jeznach
2024-10-01 23:15 ` Daniel Henrique Barboza
2024-09-24 22:17 ` [PULL v2 17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device Alistair Francis
2024-09-24 22:17 ` [PULL v2 18/47] hw/riscv: add riscv-iommu-pci reference device Alistair Francis
2024-09-24 22:17 ` [PULL v2 19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug Alistair Francis
2024-09-24 22:17 ` [PULL v2 20/47] test/qtest: add riscv-iommu-pci tests Alistair Francis
2024-09-24 22:17 ` [PULL v2 21/47] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) Alistair Francis
2024-09-24 22:17 ` [PULL v2 22/47] hw/riscv/riscv-iommu: add ATS support Alistair Francis
2024-09-24 22:17 ` [PULL v2 23/47] hw/riscv/riscv-iommu: add DBG support Alistair Francis
2024-09-24 22:17 ` [PULL v2 24/47] qtest/riscv-iommu-test: add init queues test Alistair Francis
2024-09-24 22:17 ` [PULL v2 25/47] docs/specs: add riscv-iommu Alistair Francis
2024-09-24 22:17 ` [PULL v2 26/47] hw/riscv: Respect firmware ELF entry point Alistair Francis
2024-09-24 22:17 ` [PULL v2 27/47] target: riscv: Add Svvptc extension support Alistair Francis
2024-09-24 22:17 ` [PULL v2 28/47] target/riscv32: Fix masking of physical address Alistair Francis
2024-09-24 22:17 ` [PULL v2 29/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Alistair Francis
2024-09-24 22:17 ` [PULL v2 30/47] hw/intc: riscv-imsic: Fix interrupt state updates Alistair Francis
2024-09-24 22:17 ` [PULL v2 31/47] bsd-user: Implement RISC-V CPU initialization and main loop Alistair Francis
2024-09-24 22:17 ` [PULL v2 32/47] bsd-user: Add RISC-V CPU execution loop and syscall handling Alistair Francis
2024-09-24 22:17 ` [PULL v2 33/47] bsd-user: Implement RISC-V CPU register cloning and reset functions Alistair Francis
2024-09-24 22:17 ` [PULL v2 34/47] bsd-user: Implement RISC-V TLS register setup Alistair Francis
2024-09-24 22:17 ` [PULL v2 35/47] bsd-user: Add RISC-V ELF definitions and hardware capability detection Alistair Francis
2024-09-24 22:17 ` [PULL v2 36/47] bsd-user: Define RISC-V register structures and register copying Alistair Francis
2024-09-24 22:17 ` [PULL v2 37/47] bsd-user: Add RISC-V signal trampoline setup function Alistair Francis
2024-09-24 22:17 ` [PULL v2 38/47] bsd-user: Implement RISC-V sysarch system call emulation Alistair Francis
2024-09-24 22:17 ` [PULL v2 39/47] bsd-user: Add RISC-V thread setup and initialization support Alistair Francis
2024-09-24 22:17 ` [PULL v2 40/47] bsd-user: Define RISC-V VM parameters and helper functions Alistair Francis
2024-09-24 22:17 ` [PULL v2 41/47] bsd-user: Define RISC-V system call structures and constants Alistair Francis
2024-09-24 22:17 ` [PULL v2 42/47] bsd-user: Add generic RISC-V64 target definitions Alistair Francis
2024-09-24 22:17 ` [PULL v2 43/47] bsd-user: Define RISC-V signal handling structures and constants Alistair Francis
2024-09-24 22:17 ` [PULL v2 44/47] bsd-user: Implement RISC-V signal trampoline setup functions Alistair Francis
2024-09-24 22:17 ` [PULL v2 45/47] bsd-user: Implement 'get_mcontext' for RISC-V Alistair Francis
2024-09-24 22:17 ` [PULL v2 46/47] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Alistair Francis
2024-09-24 22:17 ` [PULL v2 47/47] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Alistair Francis
2024-09-28 11:34 ` [PULL v2 00/47] riscv-to-apply queue Peter Maydell
2024-09-28 20:23 ` Peter Maydell
2024-09-28 20:40 ` Daniel Henrique Barboza
2024-09-29 15:38 ` Peter Maydell
2024-09-29 20:53 ` Daniel Henrique Barboza
2024-09-30 10:48 ` Peter Maydell
2024-09-30 12:05 ` Daniel Henrique Barboza
2024-09-30 10:58 ` Thomas Huth
2024-09-30 11:35 ` Thomas Huth
2024-10-21 16:17 ` Thomas Huth
2024-09-30 12:10 ` Ilya Leoshkevich
2024-09-30 23:04 ` Daniel Henrique Barboza [this message]
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