From: Richard Henderson <rth@twiddle.net>
To: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: peter.maydell@linaro.org, Ethan Hunt <proljc@gmail.com>,
qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode
Date: Sun, 06 Sep 2015 13:36:39 -0700 [thread overview]
Message-ID: <25f6c6b5-ea69-4f3c-9c4c-d17a8cebba45@email.android.com> (raw)
In-Reply-To: <55EB603C.70602@mail.uni-paderborn.de>
On Sep 5, 2015 14:35, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> wrote:
> IIRC a lot of the registers are supervisor only, e.g. VR, NPC or SR and
> the manual is fairly clear about that. User mode cpu ought not to read
> these registers unconditionally.
When I last discussed this on the openrisc list, back in March, there was no real specification for user mode, and what bits are or should be accessible.
Looking at
http://opencores.org/or1k/Architecture_Specification
today, that still seems to be the case.
In the meantime, dropping the privilege check makes linux-user GCC tests work better.
r~
next prev parent reply other threads:[~2015-09-06 20:36 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-03 0:17 [Qemu-devel] [PATCH 00/17] target-openrisc improvements Richard Henderson
2015-09-03 0:17 ` [Qemu-devel] [PATCH 01/17] target-openrisc: Always enable OPENRISC_DISAS Richard Henderson
2015-09-03 14:15 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 02/17] target-openrisc: Streamline arithmetic and OVE Richard Henderson
2015-09-03 14:16 ` Bastian Koppelmann
2015-09-03 14:44 ` Richard Henderson
2015-09-04 13:12 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 03/17] target-openrisc: Invert the decoding in dec_calc Richard Henderson
2015-09-03 14:48 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 04/17] target-openrisc: Keep SR_F in a separate variable Richard Henderson
2015-09-03 15:09 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 05/17] target-openrisc: Use movcond where appropriate Richard Henderson
2015-09-03 16:04 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 06/17] target-openrisc: Put SR[OVE] in TB flags Richard Henderson
2015-09-04 13:05 ` Bastian Koppelmann
2015-09-04 14:29 ` Richard Henderson
2015-09-03 0:17 ` [Qemu-devel] [PATCH 07/17] target-openrisc: Keep SR_CY and SR_OV in a separate variables Richard Henderson
2015-09-04 13:33 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 08/17] target-openrisc: Set flags on helpers Richard Henderson
2015-09-04 13:58 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 09/17] target-openrisc: Implement ff1 and fl1 for 64-bit Richard Henderson
2015-09-04 13:59 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 10/17] target-openrisc: Represent MACHI:MACLO as a single unit Richard Henderson
2015-09-04 15:04 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 11/17] target-openrisc: Rationalize immediate extraction Richard Henderson
2015-09-04 15:24 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 12/17] target-openrisc: Enable m[tf]spr from user mode Richard Henderson
2015-09-05 21:35 ` Bastian Koppelmann
2015-09-06 20:36 ` Richard Henderson [this message]
2015-09-13 8:34 ` Bastian Koppelmann
2015-09-14 17:11 ` Richard Henderson
2015-09-15 7:22 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 13/17] target-openrisc: Enable trap, csync, msync, psync for " Richard Henderson
2015-09-06 9:30 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 14/17] target-openrisc: Implement muld, muldu, macu, msbu Richard Henderson
2015-09-06 11:38 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 15/17] target-openrisc: Fix madd Richard Henderson
2015-09-13 8:21 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 16/17] target-openrisc: Write back result before FPE exception Richard Henderson
2015-09-15 13:02 ` Bastian Koppelmann
2015-09-03 0:17 ` [Qemu-devel] [PATCH 17/17] target-openrisc: Implement lwa, swa Richard Henderson
2015-09-15 13:04 ` Bastian Koppelmann
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