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From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <2619969c-866a-5d9a-ff19-800edd1815be@mail.uni-paderborn.de>
Date: Fri, 19 Oct 2018 14:49:52 +0200
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Subject: Re: [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of
 RVXC insns to decodetree
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To: Richard Henderson <richard.henderson@linaro.org>, mjc@sifive.com, palmer@sifive.com, sagark@eecs.berkeley.edu
Cc: peer.adelt@hni.uni-paderborn.de, Alistair.Francis@wdc.com, qemu-devel@nongnu.org


On 10/13/18 8:18 PM, Richard Henderson wrote:
> On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
>> +# Argument sets:
>> +&cl               rs1 rd
>> +&cl_dw     uimm   rs1 rd
>> +&ciw       nzuimm     rd
>> +&cs               rs1 rs2
>> +&cs_dw     uimm   rs1 rs2
> I guess this is good enough for now.
> What I'd like to see is something like
>
> &i	imm rs1 rd	!extern


That looks so much better. Can you CC me when you send the patches for 
the extern support, so I can implement this for RISC-V?


Cheers,

Bastian