From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: Aurelien Jarno <aurelien@aurel32.net>,
"Michael S . Tsirkin" <mst@redhat.com>
Subject: Re: [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask
Date: Thu, 1 Aug 2024 16:59:16 +0200 [thread overview]
Message-ID: <2638c0b9-659e-42fb-9830-b913e4e4354a@linaro.org> (raw)
In-Reply-To: <20240801145630.52680-3-philmd@linaro.org>
On 1/8/24 16:56, Philippe Mathieu-Daudé wrote:
> When booting Linux we see:
>
> PCI host bridge to bus 0000:00
> pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff]
> pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff]
> pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
> pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000
> pci 0000:00:00.0: [Firmware Bug]: reg 0x14: invalid BAR (can't size)
> pci 0000:00:00.0: [Firmware Bug]: reg 0x18: invalid BAR (can't size)
> pci 0000:00:00.0: [Firmware Bug]: reg 0x1c: invalid BAR (can't size)
> pci 0000:00:00.0: [Firmware Bug]: reg 0x20: invalid BAR (can't size)
> pci 0000:00:00.0: [Firmware Bug]: reg 0x24: invalid BAR (can't size)
>
> This is due to missing base address register write mask.
> Add it to get:
>
> PCI host bridge to bus 0000:00
> pci_bus 0000:00: root bus resource [mem 0x10000000-0x17ffffff]
> pci_bus 0000:00: root bus resource [io 0x1000-0x1fffff]
> pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
> pci 0000:00:00.0: [11ab:4620] type 00 class 0x060000
> pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00000fff pref]
> pci 0000:00:00.0: reg 0x14: [mem 0x01000000-0x01000fff pref]
> pci 0000:00:00.0: reg 0x18: [mem 0x1c000000-0x1c000fff]
> pci 0000:00:00.0: reg 0x1c: [mem 0x1f000000-0x1f000fff]
> pci 0000:00:00.0: reg 0x20: [mem 0x1be00000-0x1be00fff]
> pci 0000:00:00.0: reg 0x24: [io 0x14000000-0x14000007]
>
> Mention the datasheet referenced. Remove the "Malta assumptions ahead"
> comment since the reset values from the datasheet are used.
Argh this comment belongs to the previous patch :/
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/pci-host/gt64120.c | 7 +++++++
> 1 file changed, 7 insertions(+)
next prev parent reply other threads:[~2024-08-01 14:59 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-01 14:56 [PATCH-for-9.1 v2 0/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé
2024-08-01 14:56 ` [PATCH-for-9.1 v2 1/2] hw/pci-host/gt64120: Reset config registers during RESET phase Philippe Mathieu-Daudé
2024-08-01 14:56 ` [PATCH-for-9.1 v2 2/2] hw/pci-host/gt64120: Set PCI base address register write mask Philippe Mathieu-Daudé
2024-08-01 14:59 ` Philippe Mathieu-Daudé [this message]
2024-08-01 15:02 ` Michael S. Tsirkin
2024-08-01 16:51 ` Philippe Mathieu-Daudé
2024-08-01 16:51 ` Philippe Mathieu-Daudé
2024-08-01 15:03 ` Michael S. Tsirkin
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