From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 9/9] target/arm: Allow board models to specify initial NS VTOR
Date: Mon, 24 May 2021 10:05:17 -0700 [thread overview]
Message-ID: <263a44a4-a890-31fc-ab51-33c519b704f5@linaro.org> (raw)
In-Reply-To: <20210520152840.24453-10-peter.maydell@linaro.org>
On 5/20/21 8:28 AM, Peter Maydell wrote:
> Currently we allow board models to specify the initial value of the
> Secure VTOR register, using an init-svtor property on the TYPE_ARMV7M
> object which is plumbed through to the CPU. Allow board models to
> also specify the initial value of the Non-secure VTOR via a similar
> init-nsvtor property.
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> I admit to not having a publicly-visible use for this yet, but
> it does bring the NSVTOR into line with both our handling of the
> SVTOR and also with the hardware, which allows both to be set
> via reset-time config signal inputs, as seen eg on the Cortex-M55:
> https://developer.arm.com/documentation/101051/0002/Signal-descriptions/Reset-configuration-signals?lang=en
> ---
> include/hw/arm/armv7m.h | 2 ++
> target/arm/cpu.h | 2 ++
> hw/arm/armv7m.c | 7 +++++++
> target/arm/cpu.c | 10 ++++++++++
> 4 files changed, 21 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-05-24 17:47 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-20 15:28 [PATCH 0/9] target/arm: MVE preliminaries Peter Maydell
2021-05-20 15:28 ` [PATCH 1/9] target/arm: Add isar feature check functions for MVE Peter Maydell
2021-05-24 15:21 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 2/9] target/arm: Update feature checks for insns which are "MVE or FP" Peter Maydell
2021-05-24 15:32 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 3/9] target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp Peter Maydell
2021-05-24 16:24 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 4/9] target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp Peter Maydell
2021-05-24 16:31 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 5/9] target/arm: Fix return values in fp_sysreg_checks() Peter Maydell
2021-05-24 16:36 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 6/9] target/arm: Implement M-profile VPR register Peter Maydell
2021-05-24 16:51 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 7/9] target/arm: Make FPSCR.LTPSIZE writable for MVE Peter Maydell
2021-05-24 16:56 ` Richard Henderson
2021-05-20 15:28 ` [PATCH 8/9] target/arm: Enable FPSCR.QC bit " Peter Maydell
2021-05-24 16:59 ` Richard Henderson
2021-05-24 17:08 ` Peter Maydell
2021-05-20 15:28 ` [PATCH 9/9] target/arm: Allow board models to specify initial NS VTOR Peter Maydell
2021-05-24 17:05 ` Richard Henderson [this message]
2021-05-20 15:45 ` [PATCH 0/9] target/arm: MVE preliminaries no-reply
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