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Fri, 12 Dec 2025 08:28:29 -0800 (PST) Received: from [10.229.62.227] ([187.217.227.247]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cadb1d0facsm3753989a34.3.2025.12.12.08.28.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Dec 2025 08:28:29 -0800 (PST) Message-ID: <2680c481-088b-4366-abc3-7d48d90db0b5@linaro.org> Date: Fri, 12 Dec 2025 10:28:26 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH-for-11.0 v3 11/22] target/mips: Use big-endian variant of cpu_ld/st_data*() for MSA opcode To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo References: <20251126202200.23100-1-philmd@linaro.org> <20251126202200.23100-12-philmd@linaro.org> From: Richard Henderson Content-Language: en-US In-Reply-To: <20251126202200.23100-12-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/26/25 14:21, Philippe Mathieu-Daudé wrote: > MSA vectors are accessed in big endianness. > > Per the "MIPS® SIMD Architecture" (MD00926 rev 1.03): > > 3.1 Registers Layout > > MSA vectors are stored in memory starting from the 0th element at > the lowest byte address. The byte order of each element follows the > big- or little-endian convention of the system configuration. This says "follow the system configuration" ... > > Use the explicit big-endian variants of cpu_ld/st_data*(). ... so how do you get "big-endian" from that? > diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c > index f554b3d10ee..d6ce17abf9a 100644 > --- a/target/mips/tcg/msa_helper.c > +++ b/target/mips/tcg/msa_helper.c > @@ -8231,8 +8231,8 @@ void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, > uint64_t d0, d1; > > /* Load 8 bytes at a time. Vector element ordering makes this LE. */ > - d0 = cpu_ldq_le_data_ra(env, addr + 0, ra); > - d1 = cpu_ldq_le_data_ra(env, addr + 8, ra); > + d0 = cpu_ldq_be_data_ra(env, addr + 0, ra); > + d1 = cpu_ldq_be_data_ra(env, addr + 8, ra); > pwd->d[0] = d0; > pwd->d[1] = d1; This really seems to be exchanging one bug for another. And the comment no longer matches. Also, this would be much better accomplished inline as tcg_gen_ld_i128(..., mo_endian(s) | MO_128 | MO_ATOM_); where will be MO_ATOM_NONE for vector of 1-byte elements, MO_ATOM_IFALIGN_PAIR for 8-byte elements, and MO_ATOM_SUBALIGN for the others (which is slightly stronger than required, but we don't have MO_ATOM_IFALIGN_ for all N). Doing that for the stores as well will allow removal of ... > ensure_writable_pages(env, addr, mmu_idx, GETPC()); ... this hack. r~