* [Qemu-devel] [PATCH v2 1/6] target/mips: Preparing for adding MMI instructions
2019-02-26 12:23 [Qemu-devel] [PATCH v2 0/6] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
@ 2019-02-26 12:23 ` Mateja Marjanovic
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 2/6] target/mips: Add emulation of MMI instruction PCPYH Mateja Marjanovic
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Mateja Marjanovic @ 2019-02-26 12:23 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Set up MMI code to be compiled only for TARGET_MIPS64. This is
needed so that GPRs are 64 bit, and combined with MMI registers,
they will form full 128 bit registers.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
---
target/mips/translate.c | 43 +++++++++++++++++++++++++++++++++++++++++--
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3b17020..332ff79 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4362,6 +4362,7 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
+#if defined(TARGET_MIPS64)
/* Copy GPR to and from TX79 HI1/LO1 register. */
static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
{
@@ -4397,6 +4398,7 @@ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
break;
}
}
+#endif
/* Arithmetic on HI/LO registers */
static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
@@ -4746,6 +4748,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_temp_free(t1);
}
+#if defined(TARGET_MIPS64)
static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
{
TCGv t0, t1;
@@ -4802,6 +4805,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
tcg_temp_free(t0);
tcg_temp_free(t1);
}
+#endif
static void gen_muldiv(DisasContext *ctx, uint32_t opc,
int acc, int rs, int rt)
@@ -24324,6 +24328,29 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
}
+#if defined(TARGET_MIPS64)
+
+/*
+ *
+ * MMI (MultiMedia Interface) ASE instructions
+ * ===========================================
+ */
+
+/*
+ * MMI instructions category: data communication
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * PCPYH PEXCH PEXTLB PINTH PPACB PEXT5 PREVH
+ * PCPYLD PEXCW PEXTLH PINTEH PPACH PPAC5 PROT3W
+ * PCPYUD PEXCEH PEXTLW PPACW
+ * PEXCEW PEXTUB
+ * PEXTUB
+ * PEXTUB
+ */
+
+#endif
+
+
#if !defined(TARGET_MIPS64)
/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */
@@ -27247,6 +27274,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
}
+
+#if defined(TARGET_MIPS64)
+
static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_MMI0(ctx->opcode);
@@ -27491,6 +27521,8 @@ static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
gen_mmi_sq(ctx, base, rt, offset);
}
+#endif
+
static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
{
int rs, rt, rd, sa;
@@ -28796,10 +28828,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
decode_opc_special(env, ctx);
break;
case OPC_SPECIAL2:
+#if defined(TARGET_MIPS64)
if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
decode_mmi(env, ctx);
-#if !defined(TARGET_MIPS64)
- } else if (ctx->insn_flags & ASE_MXU) {
+#else
+ if (ctx->insn_flags & ASE_MXU) {
decode_opc_mxu(env, ctx);
#endif
} else {
@@ -28807,11 +28840,15 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_SPECIAL3:
+#if defined(TARGET_MIPS64)
if (ctx->insn_flags & INSN_R5900) {
decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */
} else {
decode_opc_special3(env, ctx);
}
+#else
+ decode_opc_special3(env, ctx);
+#endif
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
@@ -29483,7 +29520,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_MSA: /* OPC_MDMX */
if (ctx->insn_flags & INSN_R5900) {
+#if defined(TARGET_MIPS64)
gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */
+#endif
} else {
/* MDMX: Not implemented. */
gen_msa(env, ctx);
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [Qemu-devel] [PATCH v2 2/6] target/mips: Add emulation of MMI instruction PCPYH
2019-02-26 12:23 [Qemu-devel] [PATCH v2 0/6] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 1/6] target/mips: Preparing for adding " Mateja Marjanovic
@ 2019-02-26 12:23 ` Mateja Marjanovic
2019-02-26 17:14 ` Richard Henderson
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 3/6] target/mips: Add emulation of MMI instruction PCPYLD Mateja Marjanovic
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Mateja Marjanovic @ 2019-02-26 12:23 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PCPYH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
---
target/mips/translate.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 332ff79..0d648b6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24348,6 +24348,68 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
* PEXTUB
*/
+/*
+ * PCPYH rd, rt
+ *
+ * Parallel Copy Halfword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyh(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask = (1ULL << 16) - 1;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t1);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask);
+ tcg_gen_movi_i64(t1, 0);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_or_i64(t1, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27400,10 +27462,12 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
- case MMI_OPC_3_PCPYH: /* TODO: MMI_OPC_3_PCPYH */
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
+ case MMI_OPC_3_PCPYH:
+ gen_mmi_pcpyh(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH v2 2/6] target/mips: Add emulation of MMI instruction PCPYH
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 2/6] target/mips: Add emulation of MMI instruction PCPYH Mateja Marjanovic
@ 2019-02-26 17:14 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2019-02-26 17:14 UTC (permalink / raw)
To: Mateja Marjanovic, qemu-devel; +Cc: arikalo, amarkovic, aurelien
On 2/26/19 4:23 AM, Mateja Marjanovic wrote:
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
> + tcg_gen_movi_i64(t1, 0);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_shli_i64(t0, t0, 16);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_shli_i64(t0, t0, 16);
> + tcg_gen_or_i64(t1, t0, t1);
> + tcg_gen_shli_i64(t0, t0, 16);
> + tcg_gen_or_i64(t1, t0, t1);
See previous review about this using 4x too many operations.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 3/6] target/mips: Add emulation of MMI instruction PCPYLD
2019-02-26 12:23 [Qemu-devel] [PATCH v2 0/6] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 1/6] target/mips: Preparing for adding " Mateja Marjanovic
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 2/6] target/mips: Add emulation of MMI instruction PCPYH Mateja Marjanovic
@ 2019-02-26 12:23 ` Mateja Marjanovic
2019-02-26 17:01 ` Richard Henderson
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 4/6] target/mips: Add emulation of MMI instruction PCPYUD Mateja Marjanovic
` (2 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Mateja Marjanovic @ 2019-02-26 12:23 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
Add emulation of MMI instruction PCPYLD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
---
target/mips/translate.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0d648b6..7c26a43 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24410,6 +24410,45 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
}
}
+/*
+ * PCPYLD rd, rs, rt
+ *
+ * Parallel Copy Lower Doubleword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PCPYLD | MMI2 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyld(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ if (rs == 0) {
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
+ }
+ if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ } else {
+ if (rd != rt) {
+ tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
+ }
+ }
+ }
+}
+
#endif
@@ -27424,7 +27463,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PINTH: /* TODO: MMI_OPC_2_PINTH */
case MMI_OPC_2_PMULTW: /* TODO: MMI_OPC_2_PMULTW */
case MMI_OPC_2_PDIVW: /* TODO: MMI_OPC_2_PDIVW */
- case MMI_OPC_2_PCPYLD: /* TODO: MMI_OPC_2_PCPYLD */
case MMI_OPC_2_PMADDH: /* TODO: MMI_OPC_2_PMADDH */
case MMI_OPC_2_PHMADH: /* TODO: MMI_OPC_2_PHMADH */
case MMI_OPC_2_PAND: /* TODO: MMI_OPC_2_PAND */
@@ -27439,6 +27477,9 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
break;
+ case MMI_OPC_2_PCPYLD:
+ gen_mmi_pcpyld(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI2");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [Qemu-devel] [PATCH v2 4/6] target/mips: Add emulation of MMI instruction PCPYUD
2019-02-26 12:23 [Qemu-devel] [PATCH v2 0/6] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (2 preceding siblings ...)
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 3/6] target/mips: Add emulation of MMI instruction PCPYLD Mateja Marjanovic
@ 2019-02-26 12:23 ` Mateja Marjanovic
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 5/6] target/mips: Add emulation of MMI instruction PEXCH Mateja Marjanovic
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 6/6] target/mips: Add emulation of MMI instruction PEXCW Mateja Marjanovic
5 siblings, 0 replies; 11+ messages in thread
From: Mateja Marjanovic @ 2019-02-26 12:23 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PCPYUD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
---
target/mips/translate.c | 43 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7c26a43..dd90178 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24449,6 +24449,45 @@ static void gen_mmi_pcpyld(DisasContext *ctx)
}
}
+/*
+ * PCPYUD rd, rs, rt
+ *
+ * Parallel Copy Upper Doubleword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PCPYUD | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyud(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else {
+ if (rs == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ } else {
+ tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]);
+ }
+ if (rt == 0) {
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ if (rd != rt) {
+ tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]);
+ }
+ }
+ }
+}
+
#endif
@@ -27499,7 +27538,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PINTEH: /* TODO: MMI_OPC_3_PINTEH */
case MMI_OPC_3_PMULTUW: /* TODO: MMI_OPC_3_PMULTUW */
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
- case MMI_OPC_3_PCPYUD: /* TODO: MMI_OPC_3_PCPYUD */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
@@ -27509,6 +27547,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PCPYH:
gen_mmi_pcpyh(ctx);
break;
+ case MMI_OPC_3_PCPYUD:
+ gen_mmi_pcpyud(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [Qemu-devel] [PATCH v2 5/6] target/mips: Add emulation of MMI instruction PEXCH
2019-02-26 12:23 [Qemu-devel] [PATCH v2 0/6] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (3 preceding siblings ...)
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 4/6] target/mips: Add emulation of MMI instruction PCPYUD Mateja Marjanovic
@ 2019-02-26 12:23 ` Mateja Marjanovic
2019-02-26 17:06 ` Richard Henderson
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 6/6] target/mips: Add emulation of MMI instruction PEXCW Mateja Marjanovic
5 siblings, 1 reply; 11+ messages in thread
From: Mateja Marjanovic @ 2019-02-26 12:23 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXCH. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 97 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 96 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index dd90178..66cea86 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24488,6 +24488,99 @@ static void gen_mmi_pcpyud(DisasContext *ctx)
}
}
+/*
+ * PEXCH rd, rt
+ *
+ * Parallel Exchange Center Halfword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PEXCH | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pexch(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else if (rd == rt) {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 16) - 1;
+ uint64_t mask1 = mask0 << 16;
+ uint64_t mask2 = mask1 << 16;
+ uint64_t mask3 = (mask2 << 16) | mask0;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+
+ tcg_gen_andi_i64(cpu_gpr[rt], cpu_gpr[rt], mask3);
+ tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0);
+ tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+ tcg_gen_shli_i64(t0, t0, 16);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+
+ tcg_gen_andi_i64(cpu_mmr[rt], cpu_mmr[rt], mask3);
+ tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
+ tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 16) - 1;
+ uint64_t mask1 = mask0 << 16;
+ uint64_t mask2 = mask1 << 16;
+ uint64_t mask3 = mask2 << 16;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
+ tcg_gen_or_i64(t0, t0, t1);
+
+ tcg_gen_mov_i64(cpu_gpr[rd], t0);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
+ tcg_gen_shri_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1);
+ tcg_gen_shli_i64(t1, t1, 16);
+ tcg_gen_or_i64(t0, t0, t1);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
+ tcg_gen_or_i64(t0, t0, t1);
+
+ tcg_gen_mov_i64(cpu_mmr[rd], t0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27540,7 +27633,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
- case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
@@ -27550,6 +27642,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PCPYUD:
gen_mmi_pcpyud(ctx);
break;
+ case MMI_OPC_3_PEXCH:
+ gen_mmi_pexch(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH v2 5/6] target/mips: Add emulation of MMI instruction PEXCH
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 5/6] target/mips: Add emulation of MMI instruction PEXCH Mateja Marjanovic
@ 2019-02-26 17:06 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2019-02-26 17:06 UTC (permalink / raw)
To: Mateja Marjanovic, qemu-devel; +Cc: arikalo, amarkovic, aurelien
On 2/26/19 4:23 AM, Mateja Marjanovic wrote:
> + } else if (rd == rt) {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 16) - 1;
> + uint64_t mask1 = mask0 << 16;
> + uint64_t mask2 = mask1 << 16;
> + uint64_t mask3 = (mask2 << 16) | mask0;
> +
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> + tcg_gen_shli_i64(t0, t0, 16);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
> + tcg_gen_shri_i64(t1, t1, 16);
> +
> + tcg_gen_andi_i64(cpu_gpr[rt], cpu_gpr[rt], mask3);
> + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t0);
> + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
> + tcg_gen_shli_i64(t0, t0, 16);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
> + tcg_gen_shri_i64(t1, t1, 16);
> +
> + tcg_gen_andi_i64(cpu_mmr[rt], cpu_mmr[rt], mask3);
> + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
> + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t1);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 16) - 1;
> + uint64_t mask1 = mask0 << 16;
> + uint64_t mask2 = mask1 << 16;
> + uint64_t mask3 = mask2 << 16;
> +
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask3);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask2);
> + tcg_gen_shri_i64(t1, t1, 16);
> + tcg_gen_or_i64(t0, t0, t1);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
> + tcg_gen_shli_i64(t1, t1, 16);
> + tcg_gen_or_i64(t0, t0, t1);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
> + tcg_gen_or_i64(t0, t0, t1);
> +
> + tcg_gen_mov_i64(cpu_gpr[rd], t0);
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask3);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask2);
> + tcg_gen_shri_i64(t1, t1, 16);
> + tcg_gen_or_i64(t0, t0, t1);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask1);
> + tcg_gen_shli_i64(t1, t1, 16);
> + tcg_gen_or_i64(t0, t0, t1);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
> + tcg_gen_or_i64(t0, t0, t1);
> +
> + tcg_gen_mov_i64(cpu_mmr[rd], t0);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + }
The code for rd != rt will work just fine for rd == rt.
Why are you doubling the amount of code you are writing?
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v2 6/6] target/mips: Add emulation of MMI instruction PEXCW
2019-02-26 12:23 [Qemu-devel] [PATCH v2 0/6] target/mips: Add emulation of data communication MMI instructions Mateja Marjanovic
` (4 preceding siblings ...)
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 5/6] target/mips: Add emulation of MMI instruction PEXCH Mateja Marjanovic
@ 2019-02-26 12:23 ` Mateja Marjanovic
2019-02-26 17:14 ` Richard Henderson
5 siblings, 1 reply; 11+ messages in thread
From: Mateja Marjanovic @ 2019-02-26 12:23 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien, amarkovic, arikalo
From: Mateja Marjanovic <Mateja.Marjanovic@rt-rk.com>
Add emulation of MMI instruction PEXCW. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
---
target/mips/translate.c | 73 ++++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 72 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 66cea86..7a13841 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24581,6 +24581,75 @@ static void gen_mmi_pexch(DisasContext *ctx)
}
}
+/*
+ * PEXCW rd, rt
+ *
+ * Parallel Exchange Center Word
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI |0 0 0 0 0| rt | rd | PEXCW | MMI3 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+
+static void gen_mmi_pexcw(DisasContext *ctx)
+{
+ uint32_t pd, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ pd = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (unlikely(pd != 0)) {
+ generate_exception_end(ctx, EXCP_RI);
+ } else if (rd == 0) {
+ /* nop */
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else if (rt == rd) {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 32) - 1;
+ uint64_t mask1 = mask0 << 32;
+
+ tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
+ tcg_gen_shri_i64(t0, t0, 32);
+ tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
+ tcg_gen_shli_i64(t1, t1, 32);
+
+ tcg_gen_and_i64(cpu_mmr[rd], cpu_mmr[rd], mask1);
+ tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
+
+ tcg_gen_and_i64(cpu_gpr[rd], cpu_gpr[rd], mask0);
+ tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ } else {
+ TCGv_i64 t0 = tcg_temp_new();
+ TCGv_i64 t1 = tcg_temp_new();
+ uint64_t mask0 = (1ULL << 32) - 1;
+ uint64_t mask1 = mask0 << 32;
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
+ tcg_gen_shri_i64(t1, t1, 32);
+ tcg_gen_or_i64(cpu_mmr[rd], t0, t1);
+
+ tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
+ tcg_gen_shli_i64(t0, t0, 32);
+ tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
+ tcg_gen_or_i64(cpu_gpr[rd], t0, t1);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ }
+}
+
#endif
@@ -27633,7 +27702,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
- case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
case MMI_OPC_3_PCPYH:
@@ -27645,6 +27713,9 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PEXCH:
gen_mmi_pexch(ctx);
break;
+ case MMI_OPC_3_PEXCW:
+ gen_mmi_pexcw(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Qemu-devel] [PATCH v2 6/6] target/mips: Add emulation of MMI instruction PEXCW
2019-02-26 12:23 ` [Qemu-devel] [PATCH v2 6/6] target/mips: Add emulation of MMI instruction PEXCW Mateja Marjanovic
@ 2019-02-26 17:14 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2019-02-26 17:14 UTC (permalink / raw)
To: Mateja Marjanovic, qemu-devel; +Cc: arikalo, amarkovic, aurelien
On 2/26/19 4:23 AM, Mateja Marjanovic wrote:
> + } else if (rt == rd) {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 32) - 1;
> + uint64_t mask1 = mask0 << 32;
> +
> + tcg_gen_andi_i64(t0, cpu_gpr[rt], mask1);
> + tcg_gen_shri_i64(t0, t0, 32);
> + tcg_gen_andi_i64(t1, cpu_mmr[rt], mask0);
> + tcg_gen_shli_i64(t1, t1, 32);
> +
> + tcg_gen_and_i64(cpu_mmr[rd], cpu_mmr[rd], mask1);
> + tcg_gen_or_i64(cpu_mmr[rd], cpu_mmr[rd], t0);
> +
> + tcg_gen_and_i64(cpu_gpr[rd], cpu_gpr[rd], mask0);
> + tcg_gen_or_i64(cpu_gpr[rd], cpu_gpr[rd], t1);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new();
> + TCGv_i64 t1 = tcg_temp_new();
> + uint64_t mask0 = (1ULL << 32) - 1;
> + uint64_t mask1 = mask0 << 32;
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask1);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask1);
> + tcg_gen_shri_i64(t1, t1, 32);
> + tcg_gen_or_i64(cpu_mmr[rd], t0, t1);
> +
> + tcg_gen_andi_i64(t0, cpu_mmr[rt], mask0);
> + tcg_gen_shli_i64(t0, t0, 32);
> + tcg_gen_andi_i64(t1, cpu_gpr[rt], mask0);
> + tcg_gen_or_i64(cpu_gpr[rd], t0, t1);
> +
> + tcg_temp_free(t0);
> + tcg_temp_free(t1);
> + }
Likewise, why are you duplicating cases?
Also, this can be simplified with deposit:
tcg_gen_shri_i64(t0, cpu_gpr[rt], 32);
tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_mmu[rt], 32, 32);
tcg_gen_deposit_i64(cpu_mmu[rd], cpu_mmu[rt], t0, 0, 32);
r~
^ permalink raw reply [flat|nested] 11+ messages in thread