From: Richard Henderson <richard.henderson@linaro.org>
To: Rajnesh Kanwal <rkanwal@rivosinc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, bin.meng@windriver.com,
liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com,
apatel@ventanamicro.com, beeman@rivosinc.com,
tech-control-transfer-records@lists.riscv.org,
jason.chien@sifive.com, frank.chang@sifive.com
Subject: Re: [PATCH v3 4/6] target/riscv: Add support to record CTR entries.
Date: Tue, 5 Nov 2024 10:50:35 +0000 [thread overview]
Message-ID: <26a36129-67b7-49f7-a14c-28db0234aab5@linaro.org> (raw)
In-Reply-To: <20241104-b4-ctr_upstream_v3-v3-4-32fd3c48205f@rivosinc.com>
On 11/4/24 21:51, Rajnesh Kanwal wrote:
> +/*
> + * Indirect calls
> + * - jalr x1, rs where rs != x5;
> + * - jalr x5, rs where rs != x1;
> + * - c.jalr rs1 where rs1 != x5;
> + *
> + * Indirect jumps
> + * - jalr x0, rs where rs != x1 and rs != x5;
> + * - c.jr rs1 where rs1 != x1 and rs1 != x5.
> + *
> + * Returns
> + * - jalr rd, rs where (rs == x1 or rs == x5) and rd != x1 and rd != x5;
> + * - c.jr rs1 where rs1 == x1 or rs1 == x5.
> + *
> + * Co-routine swap
> + * - jalr x1, x5;
> + * - jalr x5, x1;
> + * - c.jalr x5.
> + *
> + * Other indirect jumps
> + * - jalr rd, rs where rs != x1, rs != x5, rd != x0, rd != x1 and rd != x5.
> + */
> +void helper_ctr_jalr(CPURISCVState *env, target_ulong src, target_ulong dest,
> + target_ulong rd, target_ulong rs1)
> +{
> + target_ulong curr_priv = env->priv;
> + bool curr_virt = env->virt_enabled;
> +
> + if ((rd == 1 && rs1 != 5) || (rd == 5 && rs1 != 1)) {
> + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_INDIRECT_CALL,
> + curr_priv, curr_virt);
> + } else if (rd == 0 && rs1 != 1 && rs1 != 5) {
> + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_INDIRECT_JUMP,
> + curr_priv, curr_virt);
> + } else if ((rs1 == 1 || rs1 == 5) && (rd != 1 && rd != 5)) {
> + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_RETURN,
> + curr_priv, curr_virt);
> + } else if ((rs1 == 1 && rd == 5) || (rs1 == 5 && rd == 1)) {
> + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_CO_ROUTINE_SWAP,
> + curr_priv, curr_virt);
> + } else {
> + riscv_ctr_add_entry(env, src, dest,
> + CTRDATA_TYPE_OTHER_INDIRECT_JUMP, curr_priv,
> + curr_virt);
> + }
> +}
All of these if's are constant at translation time.
You should move this decision tree...
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -569,6 +569,16 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
> }
> }
>
> +#ifndef CONFIG_USER_ONLY
> + if (ctx->cfg_ptr->ext_smctr || ctx->cfg_ptr->ext_ssctr) {
> + TCGv dest = tcg_constant_tl(ctx->base.pc_next + imm);
> + TCGv src = tcg_constant_tl(ctx->base.pc_next);
> + TCGv tcg_rd = tcg_constant_tl((target_ulong)rd);
> +
> + gen_helper_ctr_jal(tcg_env, src, dest, tcg_rd);
> + }
> +#endif
... here. All you need is to expose helper_ctr_add_entry().
With that,
> +void helper_ctr_popret(CPURISCVState *env, target_ulong src, target_ulong dest)
> +{
> + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_RETURN,
> + env->priv, env->virt_enabled);
> +}
> +
> +void helper_ctr_branch(CPURISCVState *env, target_ulong src, target_ulong dest,
> + target_ulong branch_taken)
> +{
> + target_ulong curr_priv = env->priv;
> + bool curr_virt = env->virt_enabled;
> +
> + if (branch_taken) {
> + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_TAKEN_BRANCH,
> + curr_priv, curr_virt);
> + } else {
> + riscv_ctr_add_entry(env, src, dest, CTRDATA_TYPE_NONTAKEN_BRANCH,
> + curr_priv, curr_virt);
> + }
> +}
these can go away, simply passing the correct CTRDATA_* constant at the right place.
r~
next prev parent reply other threads:[~2024-11-05 10:51 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-04 21:51 [PATCH v3 0/6] target/riscv: Add support for Control Transfer Records Ext Rajnesh Kanwal
2024-11-04 21:51 ` [PATCH v3 1/6] target/riscv: Remove obsolete sfence.vm instruction Rajnesh Kanwal
2024-11-04 21:51 ` [PATCH v3 2/6] target/riscv: Add Control Transfer Records CSR definitions Rajnesh Kanwal
2024-11-04 21:51 ` [PATCH v3 3/6] target/riscv: Add support for Control Transfer Records extension CSRs Rajnesh Kanwal
2024-11-04 21:51 ` [PATCH v3 4/6] target/riscv: Add support to record CTR entries Rajnesh Kanwal
2024-11-05 10:50 ` Richard Henderson [this message]
2024-11-04 21:51 ` [PATCH v3 5/6] target/riscv: Add CTR sctrclr instruction Rajnesh Kanwal
2024-11-04 21:51 ` [PATCH v3 6/6] target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs Rajnesh Kanwal
2024-11-05 10:58 ` [PATCH v3 0/6] target/riscv: Add support for Control Transfer Records Ext Richard Henderson
2024-12-04 12:59 ` Rajnesh Kanwal
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