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[2403:580a:f89b:0:e01b:92e5:d779:1bc0]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1ff59058d7dsm94278515ad.142.2024.08.06.19.43.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Aug 2024 19:43:42 -0700 (PDT) Message-ID: <26d37287-b4e3-42b8-818d-b96bcf128a75@linaro.org> Date: Wed, 7 Aug 2024 12:43:31 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 15/20] target/riscv: shadow stack mmu index for shadow stack instructions To: Deepak Gupta , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: pbonzini@redhat.com, palmer@dabbelt.com, Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com References: <20240807000652.1417776-1-debug@rivosinc.com> <20240807000652.1417776-16-debug@rivosinc.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240807000652.1417776-16-debug@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/7/24 10:06, Deepak Gupta wrote: > Shadow stack instructions shadow stack mmu index for load/stores. > `MMU_IDX_SS_ACCESS` at bit positon 3 is used as shadow stack index. > Shadow stack mmu index depend on privilege and SUM bit. If shadow stack > accesses happening in user mode, shadow stack mmu index = 0b1000. If > shaodw stack access happening in supervisor mode mmu index = 0b1001. If > shadow stack access happening in supervisor mode with SUM=1 then mmu > index = 0b1010 > > Signed-off-by: Deepak Gupta > --- > target/riscv/cpu.h | 13 ++++++++++ > target/riscv/cpu_helper.c | 3 +++ > target/riscv/insn_trans/trans_rva.c.inc | 8 ++++++ > target/riscv/insn_trans/trans_rvzicfiss.c.inc | 6 +++++ > target/riscv/internals.h | 1 + > target/riscv/translate.c | 25 +++++++++++++++++++ > 6 files changed, 56 insertions(+) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 6da94c417c..3ad220a9fe 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -615,6 +615,19 @@ FIELD(TB_FLAGS, FCFI_ENABLED, 28, 1) > FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 29, 1) > /* zicfiss needs a TB flag so that correct TB is located based on tb flags */ > FIELD(TB_FLAGS, BCFI_ENABLED, 30, 1) > +/* > + * zicfiss shadow stack is special memory on which regular stores aren't > + * allowed but shadow stack stores are allowed. Shadow stack stores can > + * happen as `sspush` or `ssamoswap` instructions. `sspush` implicitly > + * takes shadow stack address from CSR_SSP. But `ssamoswap` takes address > + * from encoded input register and it will be used by supervisor software > + * to access (read/write) user shadow stack for setting up rt_frame during > + * signal delivery. Supervisor software will do so by setting SUM=1. Thus > + * a TB flag is needed if SUM was 1 during TB generation to correctly > + * reflect memory permissions to access shadow stack user memory from > + * supervisor mode. > + */ > +FIELD(TB_FLAGS, SUM, 31, 1) This is already encoded into the mmu_idx as MMUIdx_S_SUM. r~