From: Richard Henderson <richard.henderson@linaro.org>
To: Ajeet Singh <itachis6234@gmail.com>, qemu-devel@nongnu.org
Cc: Warner Losh <imp@bsdimp.com>, Mark Corbin <mark@dibsco.co.uk>,
Ajeet Singh <itachis@FreeBSD.org>,
Jessica Clarke <jrtc27@jrtc27.com>,
Kyle Evans <kevans@FreeBSD.org>
Subject: Re: [PATCH v3 09/17] bsd-user: Add RISC-V thread setup and initialization support
Date: Tue, 27 Aug 2024 08:54:18 +1000 [thread overview]
Message-ID: <26e49a3e-76f1-4705-9322-a7825238bc60@linaro.org> (raw)
In-Reply-To: <20240824045635.8978-10-itachis@FreeBSD.org>
On 8/24/24 14:56, Ajeet Singh wrote:
> From: Mark Corbin<mark@dibsco.co.uk>
>
> Implemented functions for setting up and initializing threads in the
> RISC-V architecture.
> The 'target_thread_set_upcall' function sets up the stack pointer,
> program counter, and function argument for new threads.
> The 'target_thread_init' function initializes thread registers based on
> the provided image information.
>
> Signed-off-by: Mark Corbin<mark@dibsco.co.uk>
> Signed-off-by: Ajeet Singh<itachis@FreeBSD.org>
> Co-authored-by: Jessica Clarke<jrtc27@jrtc27.com>
> Co-authored-by: Kyle Evans<kevans@FreeBSD.org>
> ---
> bsd-user/riscv/target_arch_thread.h | 47 +++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 bsd-user/riscv/target_arch_thread.h
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2024-08-26 22:55 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-24 4:56 [PATCH v3 00/17] bsd-user: Comprehensive RISCV Support Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 01/17] bsd-user: Implement RISC-V CPU initialization and main loop Ajeet Singh
2024-08-26 21:28 ` Richard Henderson
2024-08-24 4:56 ` [PATCH v3 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions Ajeet Singh
2024-08-26 21:30 ` Richard Henderson
2024-08-24 4:56 ` [PATCH v3 04/17] bsd-user: Implement RISC-V TLS register setup Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 06/17] bsd-user: Define RISC-V register structures and register copying Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 07/17] bsd-user: Add RISC-V signal trampoline setup function Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 08/17] bsd-user: Implement RISC-V sysarch system call emulation Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 09/17] bsd-user: Add RISC-V thread setup and initialization support Ajeet Singh
2024-08-26 22:54 ` Richard Henderson [this message]
2024-08-24 4:56 ` [PATCH v3 10/17] bsd-user: Define RISC-V VM parameters and helper functions Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 11/17] bsd-user: Define RISC-V system call structures and constants Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 12/17] bsd-user: Add generic RISC-V64 target definitions Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 13/17] bsd-user: Define RISC-V signal handling structures and constants Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 14/17] bsd-user: Implement RISC-V signal trampoline setup functions Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 15/17] bsd-user: Implement 'get_mcontext' for RISC-V Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Ajeet Singh
2024-08-24 4:56 ` [PATCH v3 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Ajeet Singh
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