From: Richard Henderson <richard.henderson@linaro.org>
To: Max Filippov <jcmvbkbc@gmail.com>
Cc: qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes
Date: Wed, 8 Jul 2020 17:19:07 -0700 [thread overview]
Message-ID: <26e7179e-692c-9467-b2d2-c04c6f03b0db@linaro.org> (raw)
In-Reply-To: <CAMo8BfKLbHrJBfz64vO9Mtyz6fWL8+ZekiOzvpdYVhg58_PxpQ@mail.gmail.com>
On 7/8/20 10:37 AM, Max Filippov wrote:
> On Wed, Jul 8, 2020 at 9:25 AM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 7/6/20 4:47 PM, Max Filippov wrote:
>>> +float64 HELPER(add_d)(CPUXtensaState *env, float64 a, float64 b)
>>> +{
>>> + set_use_first_nan(true, &env->fp_status);
>>> + return float64_add(a, b, &env->fp_status);
>>> +}
>>> +
>>> float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
>>> {
>>> + set_use_first_nan(env->config->use_first_nan, &env->fp_status);
>>> return float32_add(a, b, &env->fp_status);
>>> }
>>
>> I think you can do better than to set the use_first_nan flag before every
>> operation.
>
> And it was better, until I found that the rules for float64 are a
> bit... peculiar.
Do I read that right,
> @@ -99,6 +103,7 @@
> XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
> XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
> XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
> + XCHAL_OPTION(XCHAL_HAVE_DFP, XTENSA_OPTION_DFP_COPROCESSOR) | \
> XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
> XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
> XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
> @@ -515,6 +520,7 @@
> .ndepc = (XCHAL_XEA_VERSION >= 2), \
> .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \
> .max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
> + .use_first_nan = !XCHAL_HAVE_DFP, \
> EXCEPTIONS_SECTION, \
> INTERRUPTS_SECTION, \
> TLB_SECTION, \
means that if DFP is present, float64 has use_first_nan, but float32 does not?!?
What in the world is going on?
>> E.g. the translator could remember the previous setting within the TB, only
>> changing when necessary. E.g. if env->config->use_first_nan, then set it
>> during reset and never change it again. Similarly if DFP is not enabled.
>
> This thought crossed my mind too, but then set_use_first_nan only
> sets one variable in the float_status and gets inlined.
> Is it worth the trouble?
You have a point that the operation I'm trying to avoid is trivial, and
probably not worth much. But I had hoped that a given cpu would stick with one
method and not change it.
r~
next prev parent reply other threads:[~2020-07-09 0:20 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-06 23:47 [PATCH 00/21] target/xtensa: implement double precision FPU Max Filippov
2020-07-06 23:47 ` [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property Max Filippov
2020-07-07 10:28 ` Alex Bennée
2020-07-08 17:41 ` Philippe Mathieu-Daudé
2020-07-06 23:47 ` [PATCH 02/21] softfloat: pass float_status pointer to pickNaN Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-06 23:47 ` [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-08 16:07 ` Richard Henderson
2020-07-08 18:11 ` Max Filippov
2020-07-06 23:47 ` [PATCH 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name Max Filippov
2020-07-06 23:47 ` [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide Max Filippov
2020-07-08 16:14 ` Richard Henderson
2020-07-08 17:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 06/21] target/xtensa: rename FPU2000 translators and helpers Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 07/21] target/xtensa: move FSR/FCR register accessors Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 08/21] target/xtensa: don't access BR regfile directly Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes Max Filippov
2020-07-08 16:25 ` Richard Henderson
2020-07-08 17:37 ` Max Filippov
2020-07-09 0:19 ` Richard Henderson [this message]
2020-07-09 5:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 10/21] target/xtensa: implement FPU division and square root Max Filippov
2020-07-06 23:47 ` [PATCH 11/21] tests/tcg/xtensa: fix test execution on ISS Max Filippov
2020-07-06 23:47 ` [PATCH 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 13/21] tests/tcg/xtensa: expand madd tests Max Filippov
2020-07-06 23:47 ` [PATCH 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 15/21] tests/tcg/xtensa: update test_fp1 " Max Filippov
2020-07-06 23:47 ` [PATCH 16/21] tests/tcg/xtensa: update test_lsc " Max Filippov
2020-07-06 23:47 ` [PATCH 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests Max Filippov
2020-07-06 23:47 ` [PATCH 18/21] tests/tcg/xtensa: test double precision load/store Max Filippov
2020-07-06 23:47 ` [PATCH 19/21] tests/tcg/xtensa: add DFP0 arith tests Max Filippov
2020-07-06 23:47 ` [PATCH 20/21] target/xtensa: import DE_233L_FPU core Max Filippov
2020-07-06 23:47 ` [PATCH 21/21] target/xtensa: import DSP3400 core Max Filippov
2020-07-07 11:31 ` [PATCH 00/21] target/xtensa: implement double precision FPU Alex Bennée
2020-07-07 16:56 ` Max Filippov
2020-07-07 19:21 ` Alex Bennée
2020-07-07 23:14 ` Max Filippov
2020-07-08 8:50 ` Alex Bennée
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