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From: Marcel Apfelbaum <marcel@redhat.com>
To: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
	Laszlo Ersek <lersek@redhat.com>,
	qemu-devel@nongnu.org, mst@redhat.com,
	"Dr. David Alan Gilbert" <dgilbert@redhat.com>
Subject: Re: [Qemu-devel] [PATCH] pci: allow 32-bit PCI IO accesses to pass through the PCI bridge
Date: Sun, 24 Sep 2017 18:43:55 +0300	[thread overview]
Message-ID: <26f60ea0-199e-f9ec-5b1d-d7023d60bb03@redhat.com> (raw)
In-Reply-To: <4a9754d9-e73b-8e67-427e-9624d0486c91@ilande.co.uk>

On 23/09/2017 11:23, Mark Cave-Ayland wrote:
> On 22/09/17 23:18, Laszlo Ersek wrote:
> 
>> On 09/22/17 14:18, Mark Cave-Ayland wrote:
>>> Whilst the underlying PCI bridge implementation supports 32-bit PCI IO
>>> accesses, unfortunately they are truncated at the legacy 64K limit.
>>>
>>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>>> ---
>>>   hw/pci/pci_bridge.c |    3 ++-
>>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
>>> index 17feae5..a47d257 100644
>>> --- a/hw/pci/pci_bridge.c
>>> +++ b/hw/pci/pci_bridge.c
>>> @@ -379,7 +379,8 @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename)
>>>       sec_bus->address_space_mem = &br->address_space_mem;
>>>       memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
>>>       sec_bus->address_space_io = &br->address_space_io;
>>> -    memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io", 65536);
>>> +    memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
>>> +                       UINT32_MAX);
>>>       br->windows = pci_bridge_region_init(br);
>>>       QLIST_INIT(&sec_bus->child);
>>>       QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
>>>
>>

Hi Mark,

>> Based on the commit message, I assume this change is guest-visible. If
>> so, should it be made dependent on a compat property, so that it doesn't
>> cause problems with migration?
> 
> In order to enable 32-bit IO accesses the PCI bridge needs to set bit 0
> in the IO_LIMIT and IO_BASE registers - this bit is read-only to guests,
> so unless a PCI bridge has this bit set then it's impossible for this
> change to be guest visible.
> 
> I did a grep for PCI_IO_RANGE_TYPE_32 and didn't see any existing users
> (other than an upcoming patchset from me!), so this combined with the
> fact that without this patch the feature is broken makes me think that I
> am the first user and so existing guests won't have a problem.
> 

(adding Dave for his expertise)

Do you know how the migration code will behave if it will have
a 65k address space on source and MAX UINT on destination?
(and the other way around for rolling back)

Thanks,
Marcel

> 
> ATB,
> 
> Mark.
> 

  reply	other threads:[~2017-09-24 15:44 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-22 12:18 [Qemu-devel] [PATCH] pci: allow 32-bit PCI IO accesses to pass through the PCI bridge Mark Cave-Ayland
2017-09-22 21:21 ` Richard Henderson
2017-09-22 22:18 ` Laszlo Ersek
2017-09-23  8:23   ` Mark Cave-Ayland
2017-09-24 15:43     ` Marcel Apfelbaum [this message]
2017-09-24 16:56       ` Mark Cave-Ayland
2017-09-25  8:11       ` Dr. David Alan Gilbert
2017-09-28  7:31         ` Mark Cave-Ayland
2017-09-28  7:56           ` Laszlo Ersek
2017-10-01 21:44             ` Mark Cave-Ayland
2017-10-11  6:35               ` Mark Cave-Ayland
2017-10-19  9:38                 ` Marcel Apfelbaum
2017-09-28  9:19           ` Marcel Apfelbaum
2017-10-01 21:49             ` Mark Cave-Ayland

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