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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id x11sm3801803pfn.53.2019.12.02.07.58.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Dec 2019 07:58:00 -0800 (PST) Subject: Re: [PATCH v2 5/5] target/arm: Add support for missing Jazelle system registers To: Marc Zyngier , qemu-devel@nongnu.org References: <20191201122018.25808-1-maz@kernel.org> <20191201122018.25808-6-maz@kernel.org> From: Richard Henderson Message-ID: <27089f4b-5bd3-04a9-9c16-91474a225c45@linaro.org> Date: Mon, 2 Dec 2019 07:57:58 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 In-Reply-To: <20191201122018.25808-6-maz@kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Peter Maydell , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/1/19 12:20 PM, Marc Zyngier wrote: > + if (cpu_isar_feature(jazelle, cpu)) { > + ARMCPRegInfo jazelle_regs[] = { static const. Otherwise, Reviewed-by: Richard Henderson r~