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[66.27.223.101]) by smtp.gmail.com with ESMTPSA id lh15-20020a170903290f00b001d923684323sm174151plb.195.2024.02.08.12.43.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Feb 2024 12:43:35 -0800 (PST) Message-ID: <2736d6d1-5585-4bbd-82c7-a3b7f5c87fb9@linaro.org> Date: Thu, 8 Feb 2024 10:43:26 -1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 03/13] target/hppa: Fix PSW_W and PSW_E bits in rsm, ssm and mtsm Content-Language: en-US To: deller@kernel.org, qemu-devel@nongnu.org Cc: Helge Deller References: <20240207182023.36316-1-deller@kernel.org> <20240207182023.36316-4-deller@kernel.org> From: Richard Henderson In-Reply-To: <20240207182023.36316-4-deller@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/7/24 08:20, deller@kernel.org wrote: > #define PSW_E 0x04000000 > +#define PSW_E_BIT 37 /* PA2.0 only */ > #define PSW_W 0x08000000 /* PA2.0 only */ > +#define PSW_W_BIT 36 /* PA2.0 only */ ... > +target_ulong HELPER(get_system_mask)(CPUHPPAState *env) > +{ > + target_ulong psw = env->psw; > + > + /* mask out invalid bits */ > + target_ulong psw_new = psw & PSW_SM; > + > + /* ssm/rsm instructions number PSW_W and PSW_E differently */ > + psw_new &= ~PSW_W; > + if (psw & PSW_W) { > + psw_new |= 1ull << (63 - PSW_W_BIT); > + } Um, this has changed nothing, since 1 << (63 - 36) == 0x8000000 == PSW_W. The conversion of PSW_SM_W to PSW_W happens in expand_sm_imm(). There's a comment there about keeping unimplemented bits disabled, including PSW_E. Perhaps this is the wrong layer in which to do this? In any case, what is the actual problem that you're seeing? Because it *isn't* that we were not considering the different placement of the bits, as your commit message suggests. > diff --git a/target/hppa/translate.c b/target/hppa/translate.c > index 53ec57ee86..10fdc0813d 100644 > --- a/target/hppa/translate.c > +++ b/target/hppa/translate.c > @@ -2163,13 +2163,20 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a) > nullify_over(ctx); > > tmp = tcg_temp_new_i64(); > - tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); > - tcg_gen_andi_i64(tmp, tmp, ~a->i); > - gen_helper_swap_system_mask(tmp, tcg_env, tmp); > - save_gpr(ctx, a->t, tmp); > + if (a->t != 0) { > + gen_helper_get_system_mask(tmp, tcg_env); > + save_gpr(ctx, a->t, tmp); > + } If a->t == 0, tmp is uninitialized... > + > + if (a->i) { > + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); ... but read here. > @@ -2183,11 +2190,17 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a) > nullify_over(ctx); > > tmp = tcg_temp_new_i64(); > - tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); > - tcg_gen_ori_i64(tmp, tmp, a->i); > - gen_helper_swap_system_mask(tmp, tcg_env, tmp); > - save_gpr(ctx, a->t, tmp); > + if (a->t != 0) { > + gen_helper_get_system_mask(tmp, tcg_env); > + save_gpr(ctx, a->t, tmp); > + } > + > + if (a->i) { > + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); > + tcg_gen_ori_i64(tmp, tmp, a->i); Likewise. r~