From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm <qemu-arm@nongnu.org>,
"QEMU Developers" <qemu-devel@nongnu.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: Re: [PATCH v2 10/12] target/arm: Optimize MVE VSHLL and VMOVL
Date: Mon, 13 Sep 2021 08:56:55 -0700 [thread overview]
Message-ID: <275b7dc6-45ed-ed32-a130-0c30a22b4960@linaro.org> (raw)
In-Reply-To: <CAFEAcA8q1Uo_79geDF3SGXt04RUSmo90+UumLxjOCAPX4HLb9g@mail.gmail.com>
On 9/13/21 7:22 AM, Peter Maydell wrote:
> On Mon, 13 Sept 2021 at 15:04, Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> On 9/13/21 2:54 AM, Peter Maydell wrote:
>>> Optimize the MVE VSHLL insns by using TCG vector ops when possible.
>>> This includes the VMOVL insn, which we handle in mve.decode as "VSHLL
>>> with zero shift count".
>>>
>>> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
>>> ---
>>> The cases here that I've implemented with ANDI then shift
>>> could also be implemented as shift-then-shift. Is one better
>>> than another?
>>
>> I would expect and + shift to be preferred over shift + shift.
>
> OK. (I wasn't sure, because and + shift requires another insn
> to assemble the immediate constant, I think.)
Yea, though Arm itself is good about not requiring one. But there's generally only one
shifter across multiple pipelines. Not that we're doing any sort of compute resource
allocation and scheduling...
r~
next prev parent reply other threads:[~2021-09-13 16:01 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 9:54 [PATCH v2 00/12] target/arm: Use TCG vector ops for MVE Peter Maydell
2021-09-13 9:54 ` [PATCH v2 01/12] target/arm: Avoid goto_tb if we're trying to exit to the main loop Peter Maydell
2021-09-13 13:36 ` Richard Henderson
2021-09-13 9:54 ` [PATCH v2 02/12] target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration Peter Maydell
2021-09-13 13:39 ` Richard Henderson
2021-09-13 9:54 ` [PATCH v2 03/12] target/arm: Add TB flag for "MVE insns not predicated" Peter Maydell
2021-09-13 13:44 ` Richard Henderson
2021-09-13 9:54 ` [PATCH v2 04/12] target/arm: Optimize MVE logic ops Peter Maydell
2021-09-13 9:54 ` [PATCH v2 05/12] target/arm: Optimize MVE arithmetic ops Peter Maydell
2021-09-13 9:54 ` [PATCH v2 06/12] target/arm: Optimize MVE VNEG, VABS Peter Maydell
2021-09-13 9:54 ` [PATCH v2 07/12] target/arm: Optimize MVE VDUP Peter Maydell
2021-09-13 13:46 ` Richard Henderson
2021-09-13 9:54 ` [PATCH v2 08/12] target/arm: Optimize MVE VMVN Peter Maydell
2021-09-13 13:47 ` Richard Henderson
2021-09-13 9:54 ` [PATCH v2 09/12] target/arm: Optimize MVE VSHL, VSHR immediate forms Peter Maydell
2021-09-13 13:56 ` Richard Henderson
2021-09-13 14:21 ` Peter Maydell
2021-09-13 15:53 ` Richard Henderson
2021-09-16 10:01 ` Peter Maydell
2021-09-16 14:39 ` Richard Henderson
2021-09-13 9:54 ` [PATCH v2 10/12] target/arm: Optimize MVE VSHLL and VMOVL Peter Maydell
2021-09-13 14:04 ` Richard Henderson
2021-09-13 14:22 ` Peter Maydell
2021-09-13 15:56 ` Richard Henderson [this message]
2021-09-13 9:54 ` [PATCH v2 11/12] target/arm: Optimize MVE VSLI and VSRI Peter Maydell
2021-09-13 14:04 ` Richard Henderson
2021-09-13 9:54 ` [PATCH v2 12/12] target/arm: Optimize MVE 1op-immediate insns Peter Maydell
2021-09-13 14:09 ` Richard Henderson
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