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Mon, 13 Sep 2021 08:56:57 -0700 (PDT) Received: from [192.168.1.11] ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id q2sm7376271pjo.27.2021.09.13.08.56.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Sep 2021 08:56:56 -0700 (PDT) Subject: Re: [PATCH v2 10/12] target/arm: Optimize MVE VSHLL and VMOVL To: Peter Maydell References: <20210913095440.13462-1-peter.maydell@linaro.org> <20210913095440.13462-11-peter.maydell@linaro.org> <0bcbd02d-abb6-de1c-efc3-d0ba465cdb9b@linaro.org> From: Richard Henderson Message-ID: <275b7dc6-45ed-ed32-a130-0c30a22b4960@linaro.org> Date: Mon, 13 Sep 2021 08:56:55 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.969, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm , QEMU Developers , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/13/21 7:22 AM, Peter Maydell wrote: > On Mon, 13 Sept 2021 at 15:04, Richard Henderson > wrote: >> >> On 9/13/21 2:54 AM, Peter Maydell wrote: >>> Optimize the MVE VSHLL insns by using TCG vector ops when possible. >>> This includes the VMOVL insn, which we handle in mve.decode as "VSHLL >>> with zero shift count". >>> >>> Signed-off-by: Peter Maydell >>> --- >>> The cases here that I've implemented with ANDI then shift >>> could also be implemented as shift-then-shift. Is one better >>> than another? >> >> I would expect and + shift to be preferred over shift + shift. > > OK. (I wasn't sure, because and + shift requires another insn > to assemble the immediate constant, I think.) Yea, though Arm itself is good about not requiring one. But there's generally only one shifter across multiple pipelines. Not that we're doing any sort of compute resource allocation and scheduling... r~