From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48380) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bwVfy-0005vr-MW for qemu-devel@nongnu.org; Tue, 18 Oct 2016 10:47:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bwVft-0003bE-I0 for qemu-devel@nongnu.org; Tue, 18 Oct 2016 10:47:34 -0400 Received: from 1.mo177.mail-out.ovh.net ([178.33.107.143]:45142) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1bwVft-0003aF-8r for qemu-devel@nongnu.org; Tue, 18 Oct 2016 10:47:29 -0400 Received: from player716.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo177.mail-out.ovh.net (Postfix) with ESMTP id 874BA1F4B for ; Tue, 18 Oct 2016 16:47:26 +0200 (CEST) References: <1475479496-16158-1-git-send-email-clg@kaod.org> <1475479496-16158-17-git-send-email-clg@kaod.org> <20161014061816.GR28562@umbus> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <276f7c4c-a3cd-489f-4d08-ed6b42c72a01@kaod.org> Date: Tue, 18 Oct 2016 16:47:19 +0200 MIME-Version: 1.0 In-Reply-To: <20161014061816.GR28562@umbus> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v4 16/20] ppc/pnv: add a XICS native to each PowerNV chip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org On 10/14/2016 08:18 AM, David Gibson wrote: > On Mon, Oct 03, 2016 at 09:24:52AM +0200, C=E9dric Le Goater wrote: >> and also link the XICS object to each core as it is needed to do the >> CPU setup. >> >> Signed-off-by: C=E9dric Le Goater >> --- >> hw/ppc/pnv.c | 18 ++++++++++++++++++ >> hw/ppc/pnv_core.c | 25 +++++++++++++++++++++---- >> include/hw/ppc/pnv.h | 2 ++ >> 3 files changed, 41 insertions(+), 4 deletions(-) >> >> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c >> index 4a71b18bf38b..6335ca11efe7 100644 >> --- a/hw/ppc/pnv.c >> +++ b/hw/ppc/pnv.c >> @@ -32,6 +32,7 @@ >> #include "exec/address-spaces.h" >> #include "qemu/cutils.h" >> =20 >> +#include "hw/ppc/xics.h" >> #include "hw/ppc/pnv_xscom.h" >> =20 >> #include "hw/isa/isa.h" >> @@ -223,6 +224,7 @@ static void powernv_populate_chip(PnvChip *chip, v= oid *fdt) >> char *typename =3D pnv_core_typename(pcc->cpu_model); >> size_t typesize =3D object_type_get_instance_size(typename); >> int i; >> + int smt =3D 1; /* TCG does not support more for the moment */ >> =20 >> pnv_xscom_populate(chip, fdt, 0); >> =20 >> @@ -230,6 +232,9 @@ static void powernv_populate_chip(PnvChip *chip, v= oid *fdt) >> PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); >> =20 >> powernv_create_core_node(chip, pnv_core, fdt); >> + >> + /* Interrupt presentation controllers (ICP). One per core. */ >> + xics_native_populate_icp(chip, fdt, 0, pnv_core->pir, smt); >> } >> =20 >> /* Put all the memory in one node on chip 0 until we find a way t= o >> @@ -631,6 +636,9 @@ static void pnv_chip_init(Object *obj) >> =20 >> object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); >> object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); >> + >> + object_initialize(&chip->xics, sizeof(chip->xics), TYPE_XICS_NATI= VE); >> + object_property_add_child(obj, "xics", OBJECT(&chip->xics), NULL)= ; >> } >> =20 >> static void pnv_chip_realize(DeviceState *dev, Error **errp) >> @@ -641,6 +649,7 @@ static void pnv_chip_realize(DeviceState *dev, Err= or **errp) >> char *typename =3D pnv_core_typename(pcc->cpu_model); >> size_t typesize =3D object_type_get_instance_size(typename); >> int i, core_hwid; >> + int smt =3D 1; /* TCG does not support more for the moment */ >> =20 >> if (!object_class_by_name(typename)) { >> error_setg(errp, "Unable to find PowerNV CPU Core '%s'", type= name); >> @@ -662,6 +671,13 @@ static void pnv_chip_realize(DeviceState *dev, Er= ror **errp) >> return; >> } >> =20 >> + /* Set up Interrupt Controller before we create the VCPUs */ >> + object_property_set_int(OBJECT(&chip->xics), smp_cpus * smt / smp= _threads, >> + "nr_servers", &error_fatal); >=20 > / smp_threads doesn't look right (more actual threads means less > servers). I think you just want smp_cpus * smp_threads. Or actually=20 > cores_per_chip * smp_threads. yes this is a left over, working because everything is 1. So yes, it will= be chip->nr_cores * smp_threads Thanks, C.=20 >> + object_property_set_bool(OBJECT(&chip->xics), true, "realized", >> + &error_fatal); >> + sysbus_mmio_map(SYS_BUS_DEVICE(&chip->xics), 0, PNV_XICS_BASE); >> + >> chip->cores =3D g_malloc0(typesize * chip->nr_cores); >> =20 >> for (i =3D 0, core_hwid =3D 0; (core_hwid < sizeof(chip->cores_ma= sk) * 8) >> @@ -684,6 +700,8 @@ static void pnv_chip_realize(DeviceState *dev, Err= or **errp) >> object_property_set_int(OBJECT(pnv_core), >> pcc->core_pir(chip, core_hwid), >> "pir", &error_fatal); >> + object_property_add_const_link(OBJECT(pnv_core), "xics", >> + OBJECT(&chip->xics), &error_fa= tal); >> object_property_set_bool(OBJECT(pnv_core), true, "realized", >> &error_fatal); >> object_unref(OBJECT(pnv_core)); >> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c >> index a1c8a14f06b6..fe18e3150f78 100644 >> --- a/hw/ppc/pnv_core.c >> +++ b/hw/ppc/pnv_core.c >> @@ -24,6 +24,7 @@ >> #include "hw/ppc/ppc.h" >> #include "hw/ppc/pnv.h" >> #include "hw/ppc/pnv_core.h" >> +#include "hw/ppc/xics.h" >> =20 >> static void powernv_cpu_reset(void *opaque) >> { >> @@ -54,7 +55,7 @@ static void powernv_cpu_reset(void *opaque) >> env->msr |=3D MSR_HVB; /* Hypervisor mode */ >> } >> =20 >> -static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp) >> +static void powernv_cpu_init(PowerPCCPU *cpu, XICSState *xics, Error = **errp) >> { >> CPUPPCState *env =3D &cpu->env; >> =20 >> @@ -63,6 +64,12 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error= **errp) >> =20 >> qemu_register_reset(powernv_cpu_reset, cpu); >> powernv_cpu_reset(cpu); >> + >> + /* >> + * XICS native cpu_setup() expects SPR_PIR to be set. So it needs >> + * to run after powernv_cpu_reset() >> + */ >> + xics_cpu_setup(xics, cpu); >> } >> =20 >> /* >> @@ -110,7 +117,7 @@ static const MemoryRegionOps pnv_core_xscom_ops =3D= { >> .endianness =3D DEVICE_BIG_ENDIAN, >> }; >> =20 >> -static void pnv_core_realize_child(Object *child, Error **errp) >> +static void pnv_core_realize_child(Object *child, XICSState *xics, Er= ror **errp) >> { >> Error *local_err =3D NULL; >> CPUState *cs =3D CPU(child); >> @@ -122,7 +129,7 @@ static void pnv_core_realize_child(Object *child, = Error **errp) >> return; >> } >> =20 >> - powernv_cpu_init(cpu, &local_err); >> + powernv_cpu_init(cpu, xics, &local_err); >> if (local_err) { >> error_propagate(errp, local_err); >> return; >> @@ -140,6 +147,7 @@ static void pnv_core_realize(DeviceState *dev, Err= or **errp) >> void *obj; >> int i, j; >> char name[32]; >> + XICSState *xics; >> =20 >> pc->threads =3D g_malloc0(size * cc->nr_threads); >> for (i =3D 0; i < cc->nr_threads; i++) { >> @@ -157,10 +165,19 @@ static void pnv_core_realize(DeviceState *dev, E= rror **errp) >> object_unref(obj); >> } >> =20 >> + /* get XICS object from chip */ >> + obj =3D object_property_get_link(OBJECT(dev), "xics", &local_err)= ; >> + if (!obj) { >> + error_setg(errp, "%s: required link 'xics' not found: %s", >> + __func__, error_get_pretty(local_err)); >> + return; >> + } >> + xics =3D XICS_COMMON(obj); >> + >> for (j =3D 0; j < cc->nr_threads; j++) { >> obj =3D pc->threads + j * size; >> =20 >> - pnv_core_realize_child(obj, &local_err); >> + pnv_core_realize_child(obj, xics, &local_err); >> if (local_err) { >> goto err; >> } >> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h >> index 3f24b87d199b..73d26c55d993 100644 >> --- a/include/hw/ppc/pnv.h >> +++ b/include/hw/ppc/pnv.h >> @@ -23,6 +23,7 @@ >> #include "hw/sysbus.h" >> #include "hw/ppc/pnv_xscom.h" >> #include "hw/ppc/pnv_lpc.h" >> +#include "hw/ppc/xics.h" >> =20 >> #define TYPE_PNV_CHIP "powernv-chip" >> #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) >> @@ -55,6 +56,7 @@ typedef struct PnvChip { >> void *cores; >> =20 >> PnvLpcController lpc; >> + XICSNative xics; >> } PnvChip; >> =20 >> typedef struct PnvChipClass { >=20