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[120.151.179.201]) by smtp.gmail.com with ESMTPSA id l26sm15342635pgm.73.2022.01.25.13.42.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Jan 2022 13:42:54 -0800 (PST) Subject: Re: [PATCH v2 2/2] target/riscv: Add XVentanaCondOps custom extension To: Philipp Tomsich , qemu-devel@nongnu.org References: <20220113202033.3320854-1-philipp.tomsich@vrull.eu> <20220113202033.3320854-2-philipp.tomsich@vrull.eu> From: Richard Henderson Message-ID: <279dadc7-496b-6b04-a011-b5eb27162cf7@linaro.org> Date: Wed, 26 Jan 2022 08:42:47 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20220113202033.3320854-2-philipp.tomsich@vrull.eu> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::536 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Bin Meng , Greg Favor , Palmer Dabbelt , Alistair Francis , Kito Cheng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 1/14/22 7:20 AM, Philipp Tomsich wrote: > new file mode 100644 > index 0000000000..b8a5d031b5 > --- /dev/null > +++ b/target/riscv/insn_trans/trans_xventanacondops.inc The filename suffix should be ".c.inc". > +static bool gen_condmask(DisasContext *ctx, arg_r *a, TCGCond cond) > +{ > + TCGv dest = dest_gpr(ctx, a->rd); > + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); > + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); > + > + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero); > + > + gen_set_gpr(ctx, a->rd, dest); > + return true; > +} > + > +static bool trans_vt_maskc(DisasContext *ctx, arg_r *a) > +{ > + return gen_condmask(ctx, a, TCG_COND_NE); > +} > + > +static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a) > +{ > + return gen_condmask(ctx, a, TCG_COND_EQ); > +} Implementation looks good. > +#define MATERIALISE_EXT_PREDICATE(ext) \ > + static inline bool has_ ## ext ## _p(CPURISCVState *env, \ > + DisasContext *ctx __attribute__((__unused__))) \ > + { \ > + return RISCV_CPU(ctx->cs)->cfg.ext_ ## ext ; \ > + } Again, no inline. Don't look back to RISCV_CPU here. We shouldn't even have access to that here, as it leads to temptation to do invalid things at translation time (this isn't one of them, since it only accesses constant state). What we have been doing is copying ext_foo into DisasContext in riscv_tr_init_disas_context. Though it might be time to revisit that. Perhaps give the cpu->cfg structure type a name, e.g. RISCVCPUConfig. Add "const RISCVCPUConfig *cfg" to DisasContext and copy the pointer across in init_disas_context. r~