* [PATCH] hw/pci: Use correct bus aperture for device container size
@ 2025-11-24 11:47 Philippe Mathieu-Daudé
2025-11-25 15:45 ` Yodel Eldar via
0 siblings, 1 reply; 2+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-11-24 11:47 UTC (permalink / raw)
To: qemu-devel
Cc: Marcel Apfelbaum, Jason Wang, Gustavo Romero, Michael S. Tsirkin,
Paolo Bonzini, Peter Maydell, Philippe Mathieu-Daudé
Before commit 3716d5902d7 ("pci: introduce a bus master container")
device view of the bus address space was correctly sized to the
bus aperture, but then it always used a 64-bit aperture. Restore
the previous behavior, so devices on 32-bit PCI only see 32-bit
address space.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/pci/pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index b1eba348e06..64f33b9de04 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1375,7 +1375,8 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
- "bus master container", UINT64_MAX);
+ "bus master container",
+ memory_region_size(bus->address_space_mem));
address_space_init(&pci_dev->bus_master_as,
&pci_dev->bus_master_container_region, pci_dev->name);
pci_dev->bus_master_as.max_bounce_buffer_size =
--
2.51.0
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] hw/pci: Use correct bus aperture for device container size
2025-11-24 11:47 [PATCH] hw/pci: Use correct bus aperture for device container size Philippe Mathieu-Daudé
@ 2025-11-25 15:45 ` Yodel Eldar via
0 siblings, 0 replies; 2+ messages in thread
From: Yodel Eldar via @ 2025-11-25 15:45 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Marcel Apfelbaum, Jason Wang, Gustavo Romero, Michael S. Tsirkin,
Paolo Bonzini, Peter Maydell
Hi, Philippe!
On 24/11/2025 05:47, Philippe Mathieu-Daudé wrote:
> Before commit 3716d5902d7 ("pci: introduce a bus master container")
> device view of the bus address space was correctly sized to the
> bus aperture, but then it always used a 64-bit aperture. Restore
> the previous behavior, so devices on 32-bit PCI only see 32-bit
> address space.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/pci/pci.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index b1eba348e06..64f33b9de04 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -1375,7 +1375,8 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev,
> pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
>
> memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev),
> - "bus master container", UINT64_MAX);
> + "bus master container",
> + memory_region_size(bus->address_space_mem));
> address_space_init(&pci_dev->bus_master_as,
> &pci_dev->bus_master_container_region, pci_dev->name);
> pci_dev->bus_master_as.max_bounce_buffer_size =
Acked-by: Yodel Eldar <yodel.eldar@yodel.dev>
Thanks,
Yodel
^ permalink raw reply [flat|nested] 2+ messages in thread
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2025-11-25 15:45 ` Yodel Eldar via
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