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Wed, 27 May 2020 09:58:27 +0800 Subject: Re: [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU To: Alistair Francis References: <24ba2634ff761e7a1e6b28b15929b03db3f59008.1589923785.git.alistair.francis@wdc.com> <2c695b2b-a292-61ff-bd2b-5f2ff2b48271@c-sky.com> From: LIU Zhiwei Message-ID: <27acc4bd-ae60-ad7e-0efb-105d4c20e132@c-sky.com> Date: Wed, 27 May 2020 09:58:27 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.8.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/26 21:58:28 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, UNPARSEABLE_RELAY=0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt , Bin Meng , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2020/5/27 1:12, Alistair Francis wrote: > On Fri, May 22, 2020 at 12:51 AM LIU Zhiwei wrote: >> >> >> On 2020/5/20 5:31, Alistair Francis wrote: >>> Ibex is a small and efficient, 32-bit, in-order RISC-V core with >>> a 2-stage pipeline that implements the RV32IMC instruction set >>> architecture. >>> >>> For more details on lowRISC see here: >>> https://github.com/lowRISC/ibex >>> >>> Signed-off-by: Alistair Francis >>> Reviewed-by: Bin Meng >>> --- >>> target/riscv/cpu.h | 1 + >>> target/riscv/cpu.c | 10 ++++++++++ >>> 2 files changed, 11 insertions(+) >>> >>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >>> index d0e7f5b9c5..8733d7467f 100644 >>> --- a/target/riscv/cpu.h >>> +++ b/target/riscv/cpu.h >>> @@ -35,6 +35,7 @@ >>> #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") >>> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") >>> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") >>> +#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") >>> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") >>> #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") >>> #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") >>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >>> index 5eb3c02735..eb2bbc87ae 100644 >>> --- a/target/riscv/cpu.c >>> +++ b/target/riscv/cpu.c >>> @@ -156,6 +156,15 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) >>> set_feature(env, RISCV_FEATURE_PMP); >>> } >>> >>> +static void rv32imcu_nommu_cpu_init(Object *obj) >>> +{ >>> + CPURISCVState *env = &RISCV_CPU(obj)->env; >>> + set_misa(env, RV32 | RVI | RVM | RVC | RVU); >>> + set_priv_version(env, PRIV_VERSION_1_10_0); >>> + set_resetvec(env, 0x8090); >> Hi Alistair, >> >> I see all RISC-V cpus have an reset vector which acts as the first pc >> when machine boots up. >> However, the first pc is more like an attribute of a machine, not a cpu. > In general it seems to be a CPU property. I assume that some CPUs > would allow the reset vector to be selectable though, in which case it > becomes a board property. > >> Another reason is that the cpu names are a combination of ISA. >> Then the cpus from different vendors may have same ISA, with different >> reset vectors. >> >> Do you think so? > If you are worried about CPUs with different vectors we could always > make it a property in the future and have boards override it. I don't > think we need that yet (only 1 CPU is different) but it is an easy > future change. I think your are right. A cpu reset vector property is better. If there is a conflict in the future, we can add the property there. Reviewed-by: LIU Zhiwei Zhiwei > Alistair > >> Zhiwei >>> + set_feature(env, RISCV_FEATURE_PMP); >>> +} >>> + >>> static void rv32imacu_nommu_cpu_init(Object *obj) >>> { >>> CPURISCVState *env = &RISCV_CPU(obj)->env; >>> @@ -619,6 +628,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { >>> DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), >>> #if defined(TARGET_RISCV32) >>> DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), >>> + DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init), >>> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), >>> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), >>> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), >>