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From: Marc Zyngier <maz@kernel.org>
To: Gavin Shan <gshan@redhat.com>
Cc: peter.maydell@linaro.org, drjones@redhat.com,
	jthierry@redhat.com, aik@ozlabs.ru, richard.henderson@linaro.org,
	qemu-devel@nongnu.org, eric.auger@redhat.com,
	qemu-arm@nongnu.org, shan.gavin@gmail.com, pbonzini@redhat.com
Subject: Re: [PATCH v3 1/2] target/arm: Support SError injection
Date: Sun, 16 Feb 2020 12:34:47 +0000	[thread overview]
Message-ID: <27b9c2a363d69911c003fcbaed958a5a@kernel.org> (raw)
In-Reply-To: <20200214055950.62477-2-gshan@redhat.com>

Hi Gavin,

On 2020-02-14 05:59, Gavin Shan wrote:
> This supports SError injection, which will be used by "virt" board to
> simulating the behavior of NMI injection in next patch. As Peter 
> Maydell
> suggested, this adds a new interrupt (ARM_CPU_SERROR), which is 
> parallel
> to CPU_INTERRUPT_HARD. The backend depends on if kvm is enabled or not.
> kvm_vcpu_ioctl(cpu, KVM_SET_VCPU_EVENTS) is leveraged to inject SError
> or data abort to guest. When TCG is enabled, the behavior is simulated
> by injecting SError and data abort to guest.
> 
> Signed-off-by: Gavin Shan <gshan@redhat.com>
> ---
>  target/arm/cpu.c      | 69 +++++++++++++++++++++++++++++++++++--------
>  target/arm/cpu.h      | 17 ++++++-----
>  target/arm/helper.c   |  6 ++++
>  target/arm/m_helper.c |  8 +++++
>  4 files changed, 81 insertions(+), 19 deletions(-)
> 

[...]

> @@ -656,7 +682,8 @@ static void arm_cpu_set_irq(void *opaque, int irq,
> int level)
>          [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
>          [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
>          [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
> -        [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
> +        [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ,
> +        [ARM_CPU_SERROR] = CPU_INTERRUPT_SERROR,

I'm a bit concerned with this. It makes sense for a host, but doesn't
allow the SError signal to be virtualised (there should be a VSError
signal in this list that can be injected via HCR_EL2.VA, just like
VIRQ is injected by HCR_EL2.VI).

Given that people use QEMU as a development platform for hypervisors,
I'd really like this functionality to be supported from day-1.

There is also the whole RAS stuff which quite a lot of work, but let's
start at least with the full ARMv8.0 semantics.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...


  parent reply	other threads:[~2020-02-16 12:36 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14  5:59 [PATCH v3 0/2] hw/arm/virt: Simulate NMI Injection Gavin Shan
2020-02-14  5:59 ` [PATCH v3 1/2] target/arm: Support SError injection Gavin Shan
2020-02-16  3:41   ` Richard Henderson
2020-02-16 23:42     ` Gavin Shan
2020-02-16 12:34   ` Marc Zyngier [this message]
2020-02-17  2:59     ` Gavin Shan
2020-02-14  5:59 ` [PATCH v3 2/2] hw/arm/virt: Simulate NMI injection Gavin Shan

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