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Thu, 15 May 2025 15:48:11 +0000 (GMT) Message-ID: <27fe9973722d8fc025f22336c77a4a4e1a18b591.camel@linux.ibm.com> Subject: Re: [PATCH 15/50] ppc/xive: Move NSR decoding into helper functions From: Miles Glenn To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?ISO-8859-1?Q?Fr=E9d=E9ric?= Barrat , Michael Kowal , Caleb Schlossin Date: Thu, 15 May 2025 10:48:10 -0500 In-Reply-To: <20250512031100.439842-16-npiggin@gmail.com> References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-16-npiggin@gmail.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-27.el8_10) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: F6NGbNW3sRVsTmz0oydBNZCpES1PFGjQ X-Authority-Analysis: v=2.4 cv=XK4wSRhE c=1 sm=1 tr=0 ts=68260cbf cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=4UZJbdheEuQRtzx_KTAA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-GUID: 4lRB4XiZeSmcUODOjGWb3ui-QHC78fHx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE1NSBTYWx0ZWRfX7HtgRP0qBi2z DXsgCgiN0MGmE8ShHEts6eUPzpy1SmzJXYCY9VbhC++is2YNTJs4kok5n3PC8hQA2025SahuGvW Jhf8Jf06CtLN/NleXmH860DXPDzt1/cHLqAgxcP9jHr4wpPsd6Jwi5IVUvxX/9nGiHa4T1Z1hXs hiNOuAejHOqwbM2lovc0sxi93NjkEMyU6pczSNOh6HaljgySD7Qo4w6TzEgeABzReyYznoohgn2 HN8oskRwPoeI1XBKHp4mcoIruAt+EfUQ0pi0/2nHF+XAA5w9z7Y+7tfopE3DGH/anld9FgfMDSB y0ZvvGDnn+j5wBnAS+25gzg9jczqfqIIOp6VqbMbJ3lEzUXnjd1X7oIGdE9UybPvrzB4TrkLeQw mZETdhPt3jnQh7lC9/bK5yM+5kH1Zg4R590dN2vY2o/Sbmc8GQJJWwsetnXwz30/o1UXqcu8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_06,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 mlxscore=0 bulkscore=0 mlxlogscore=620 clxscore=1015 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 adultscore=0 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150155 Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote: > Rather than functions to return masks to test NSR bits, have functions > to test those bits directly. This should be no functional change, it > just makes the code more readable. > > Signed-off-by: Nicholas Piggin > --- > hw/intc/xive.c | 51 +++++++++++++++++++++++++++++++++++-------- > include/hw/ppc/xive.h | 4 ++++ > 2 files changed, 46 insertions(+), 9 deletions(-) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index bb40a69c5b..c2da23f9ea 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -25,6 +25,45 @@ > /* > * XIVE Thread Interrupt Management context > */ > +bool xive_nsr_indicates_exception(uint8_t ring, uint8_t nsr) > +{ > + switch (ring) { > + case TM_QW1_OS: > + return !!(nsr & TM_QW1_NSR_EO); > + case TM_QW2_HV_POOL: > + case TM_QW3_HV_PHYS: > + return !!(nsr & TM_QW3_NSR_HE); > + default: > + g_assert_not_reached(); > + } > +} > + > +bool xive_nsr_indicates_group_exception(uint8_t ring, uint8_t nsr) > +{ > + if ((nsr & TM_NSR_GRP_LVL) > 0) { > + g_assert(xive_nsr_indicates_exception(ring, nsr)); > + return true; > + } > + return false; > +} > + > +uint8_t xive_nsr_exception_ring(uint8_t ring, uint8_t nsr) > +{ > + /* NSR determines if pool/phys ring is for phys or pool interrupt */ > + if ((ring == TM_QW3_HV_PHYS) || (ring == TM_QW2_HV_POOL)) { > + uint8_t he = (nsr & TM_QW3_NSR_HE) >> 6; > + > + if (he == TM_QW3_NSR_HE_PHYS) { > + return TM_QW3_HV_PHYS; > + } else if (he == TM_QW3_NSR_HE_POOL) { > + return TM_QW2_HV_POOL; > + } else { > + /* Don't support LSI mode */ > + g_assert_not_reached(); > + } > + } > + return ring; > +} > > static qemu_irq xive_tctx_output(XiveTCTX *tctx, uint8_t ring) > { > @@ -48,18 +87,12 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) > > qemu_irq_lower(xive_tctx_output(tctx, ring)); > > - if (regs[TM_NSR] != 0) { > + if (xive_nsr_indicates_exception(ring, nsr)) { > uint8_t cppr = regs[TM_PIPR]; > uint8_t alt_ring; > uint8_t *alt_regs; > > - /* POOL interrupt uses IPB in QW2, POOL ring */ > - if ((ring == TM_QW3_HV_PHYS) && > - ((nsr & TM_QW3_NSR_HE) == (TM_QW3_NSR_HE_POOL << 6))) { > - alt_ring = TM_QW2_HV_POOL; > - } else { > - alt_ring = ring; > - } > + alt_ring = xive_nsr_exception_ring(ring, nsr); > alt_regs = &tctx->regs[alt_ring]; > > regs[TM_CPPR] = cppr; > @@ -68,7 +101,7 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) > * If the interrupt was for a specific VP, reset the pending > * buffer bit, otherwise clear the logical server indicator > */ > - if (!(regs[TM_NSR] & TM_NSR_GRP_LVL)) { > + if (!xive_nsr_indicates_group_exception(ring, nsr)) { > alt_regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); > } > > diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h > index 538f438681..28f0f1b79a 100644 > --- a/include/hw/ppc/xive.h > +++ b/include/hw/ppc/xive.h > @@ -365,6 +365,10 @@ static inline uint32_t xive_tctx_word2(uint8_t *ring) > return *((uint32_t *) &ring[TM_WORD2]); > } > > +bool xive_nsr_indicates_exception(uint8_t ring, uint8_t nsr); > +bool xive_nsr_indicates_group_exception(uint8_t ring, uint8_t nsr); > +uint8_t xive_nsr_exception_ring(uint8_t ring, uint8_t nsr); > + > /* > * XIVE Router > */