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[71.212.39.66]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72fe69cf267sm6929956b3a.147.2025.02.02.08.51.04 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 02 Feb 2025 08:51:04 -0800 (PST) Message-ID: <281a6120-d7e4-4607-87ba-9594b5c9c22f@linaro.org> Date: Sun, 2 Feb 2025 08:51:03 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 06/69] target/arm: Define FPCR AH, FIZ, NEP bits To: qemu-devel@nongnu.org References: <20250201164012.1660228-1-peter.maydell@linaro.org> <20250201164012.1660228-7-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20250201164012.1660228-7-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/1/25 08:39, Peter Maydell wrote: > The Armv8.7 FEAT_AFP feature defines three new control bits in > the FPCR: > * FPCR.AH: "alternate floating point mode"; this changes floating > point behaviour in a variety of ways, including: > - the sign of a default NaN is 1, not 0 > - if FPCR.FZ is also 1, denormals detected after rounding > with an unbounded exponent has been applied are flushed to zero > - FPCR.FZ does not cause denormalized inputs to be flushed to zero > - miscellaneous other corner-case behaviour changes > * FPCR.FIZ: flush denormalized numbers to zero on input for > most instructions > * FPCR.NEP: makes scalar SIMD operations merge the result with > higher vector elements in one of the source registers, instead > of zeroing the higher elements of the destination > > This commit defines the new bits in the FPCR, and allows them to be > read or written when FEAT_AFP is implemented. Actual behaviour > changes will be implemented in subsequent commits. > > Note that these are the first FPCR bits which don't appear in the > AArch32 FPSCR view of the register, and which share bit positions > with FPSR bits. > > Signed-off-by: Peter Maydell > --- > target/arm/cpu-features.h | 5 +++++ > target/arm/cpu.h | 3 +++ > target/arm/vfp_helper.c | 11 ++++++++--- > 3 files changed, 16 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson r~