From: Richard Henderson <richard.henderson@linaro.org>
To: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>, qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 1/1] target/arm: Fix SCR RES1 handling
Date: Wed, 3 Feb 2021 08:28:26 -1000 [thread overview]
Message-ID: <2858ca66-8abb-f90c-7af3-0a21801e6002@linaro.org> (raw)
In-Reply-To: <20210203165552.16306-2-michael.nawrocki@gtri.gatech.edu>
On 2/3/21 6:55 AM, michael.nawrocki--- via wrote:
> The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them
> to 1 only when there is no support for AArch32 at EL1 or above.
>
> The reset value will be 0x30 only if the CPU is AArch64-only; if there
> is support for AArch32 at EL1 or above, it will be reset to 0.
>
> Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32
> is supported at EL1 or above.
>
> Signed-off-by: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
> ---
> target/arm/cpu.h | 5 +++++
> target/arm/helper.c | 16 ++++++++++++++--
> 2 files changed, 19 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2021-02-03 18:29 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-03 16:55 [PATCH v2 0/1] target/arm: Fix SCR_EL3 migration issue michael.nawrocki--- via
2021-02-03 16:55 ` [PATCH v2 1/1] target/arm: Fix SCR RES1 handling michael.nawrocki--- via
2021-02-03 18:28 ` Richard Henderson [this message]
2021-02-08 16:41 ` Peter Maydell
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