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[174.21.81.121]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7177859a470sm2295198b3a.180.2024.09.04.20.34.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Sep 2024 20:34:04 -0700 (PDT) Message-ID: <286685da-74e3-401a-afe4-fed0831fd97c@linaro.org> Date: Wed, 4 Sep 2024 20:34:02 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 02/14] util: Add RISC-V vector extension probe in cpuinfo To: LIU Zhiwei , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bmeng.cn@gmail.com, TANG Tiancheng References: <20240904142739.854-1-zhiwei_liu@linux.alibaba.com> <20240904142739.854-3-zhiwei_liu@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240904142739.854-3-zhiwei_liu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/4/24 07:27, LIU Zhiwei wrote: > + if (info & CPUINFO_ZVE64X) { > + /* > + * Get vlenb for Vector: vsetvli rd, x0, e64. > + * VLMAX = LMUL * VLEN / SEW. > + * The "vsetvli rd, x0, e64" means "LMUL = 1, SEW = 64, rd = VLMAX", > + * so "vlenb = VLMAX * 64 / 8". > + */ > + unsigned long vlmax = 0; > + asm volatile(".insn i 0x57, 7, %0, zero, (3 << 3)" : "=r"(vlmax)); > + if (vlmax) { > + riscv_vlenb = vlmax * 8; > + assert(riscv_vlen >= 64 && !(riscv_vlen & (riscv_vlen - 1))); > + } else { > + info &= ~CPUINFO_ZVE64X; > + } > + } Surely this does not compile, since the riscv_vlen referenced in the assert does not exist. That said, I've done some experimentation and I believe there is a further simplification to be had in instead saving log2(vlenb). if (info & CPUINFO_ZVE64X) { /* * We are guaranteed by RVV-1.0 that VLEN is a power of 2. * We are guaranteed by Zve64x that VLEN >= 64, and that * EEW of {8,16,32,64} are supported. * * Cache VLEN in a convenient form. */ unsigned long vlenb; asm("csrr %0, vlenb" : "=r"(vlenb)); riscv_lg2_vlenb = ctz32(vlenb); } I'll talk about how this can be used against the next patch with vsetvl. r~