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[125.254.49.187]) by smtp.gmail.com with ESMTPSA id g8-20020a170902740800b001d0c641d220sm8473630pll.257.2023.12.25.12.34.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Dec 2023 12:34:06 -0800 (PST) Message-ID: <28671cdd-c114-489c-a1c0-be11aacb7af9@linaro.org> Date: Tue, 26 Dec 2023 07:33:59 +1100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/5] target/i386: mask high bits of CR3 in 32-bit mode To: Paolo Bonzini , qemu-devel@nongnu.org Cc: mcb30@ipxe.org, qemu-stable@nongnu.org References: <20231222175951.172669-1-pbonzini@redhat.com> <20231222175951.172669-2-pbonzini@redhat.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20231222175951.172669-2-pbonzini@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/23/23 04:59, Paolo Bonzini wrote: > CR3 bits 63:32 are ignored in 32-bit mode (either legacy 2-level > paging or PAE paging). Do this in mmu_translate() to remove > the last where get_physical_address() meaningfully drops the high > bits of the address. > > Cc: qemu-stable@nongnu.org > Suggested-by: Richard Henderson > Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2022-10-18) > Signed-off-by: Paolo Bonzini > --- > target/i386/tcg/sysemu/excp_helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~ > > diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c > index 5b86f439add..11126c860d4 100644 > --- a/target/i386/tcg/sysemu/excp_helper.c > +++ b/target/i386/tcg/sysemu/excp_helper.c > @@ -238,7 +238,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in, > /* > * Page table level 3 > */ > - pte_addr = ((in->cr3 & ~0x1f) + ((addr >> 27) & 0x18)) & a20_mask; > + pte_addr = ((in->cr3 & 0xffffffe0ULL) + ((addr >> 27) & 0x18)) & a20_mask; > if (!ptw_translate(&pte_trans, pte_addr)) { > return false; > } > @@ -306,7 +306,7 @@ static bool mmu_translate(CPUX86State *env, const TranslateParams *in, > /* > * Page table level 2 > */ > - pte_addr = ((in->cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask; > + pte_addr = ((in->cr3 & 0xfffff000ULL) + ((addr >> 20) & 0xffc)) & a20_mask; > if (!ptw_translate(&pte_trans, pte_addr)) { > return false; > }