From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34084) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buFHy-00048z-6U for qemu-devel@nongnu.org; Wed, 12 Oct 2016 04:53:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1buFHt-0003m5-4K for qemu-devel@nongnu.org; Wed, 12 Oct 2016 04:53:26 -0400 Received: from 14.mo1.mail-out.ovh.net ([178.32.97.215]:58203) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buFHs-0003ls-Uw for qemu-devel@nongnu.org; Wed, 12 Oct 2016 04:53:21 -0400 Received: from player726.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo1.mail-out.ovh.net (Postfix) with ESMTP id 7BEBA13FD4 for ; Wed, 12 Oct 2016 10:53:18 +0200 (CEST) References: <1475479496-16158-1-git-send-email-clg@kaod.org> <1475479496-16158-4-git-send-email-clg@kaod.org> <20161007043221.GS18490@umbus.fritz.box> <45ecd367-07ce-e143-cf53-e7332cc94ac2@kaod.org> <20161011102452.GH8952@umbus.fritz.box> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <28a5eb21-bea5-09f9-6f90-9770812700e1@kaod.org> Date: Wed, 12 Oct 2016 10:53:12 +0200 MIME-Version: 1.0 In-Reply-To: <20161011102452.GH8952@umbus.fritz.box> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v4 03/20] ppc/pnv: add a core mask to PnvChip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org On 10/11/2016 12:24 PM, David Gibson wrote: > On Mon, Oct 10, 2016 at 02:56:25PM +0200, C=E9dric Le Goater wrote: >> >>>> @@ -227,11 +227,44 @@ static void ppc_powernv_init(MachineState *mac= hine) >>>> snprintf(chip_name, sizeof(chip_name), "chip[%d]", CHIP_HWI= D(i)); >>>> object_property_add_child(OBJECT(pnv), chip_name, chip, &er= ror_fatal); >>>> object_property_set_int(chip, CHIP_HWID(i), "chip-id", &err= or_fatal); >>>> + object_property_set_int(chip, smp_cores, "nr-cores", &error= _fatal); >>>> + /* >>>> + * We could customize cores_mask for the chip here. May be >>>> + * using a powernv machine property, like 'num-chips'. Let = the >>>> + * chip choose the default for now. >>> >>> I don't think you need any special mechanism for this. If you just >>> remove this explicit assignment the chip default will apply, but the >>> user can alter it using -global. >> >> Using a command line with : >> >> -global powernv-chip-POWER8.cores-mask=3D0x7070 >> >> would work for one chip but not for more. Let's start with that, I wil= l=20 >> remove the comment for now. multiple chip is for later. >=20 > Well, it works for more than one chip if you want the same mask for > each of them. If you want different masks, I think you can still do > it with -set, but working out the right arguments can be a PITA. That would be the best solution but I did not find a way to address one chip object to do a "qom set". (qemu) info qom-tree=20 /machine (powernv-machine) /unattached (container) /system[0] (qemu:memory-region) /sysbus (System) /ppc_powernv.ram[0] (qemu:memory-region) /io[0] (qemu:memory-region) /peripheral-anon (container) /peripheral (container) /chip[1] (powernv-chip-POWER8) ... /chip[0] (powernv-chip-POWER8) ... =20 We will have a similar need with the ram to spread the contents on the chips.=20 C.