Re: [PATCH] target/arm: Implement FEAT_DoubleFault

[Richard Henderson <richard.henderson@linaro.org>]

On 5/31/22 08:14, Peter Maydell wrote:
> The FEAT_DoubleFault extension adds the following:
> 
>   * All external aborts on instruction fetches and translation table
>     walks for instruction fetches must be synchronous.  For QEMU this
>     is already true.
> 
>   * SCR_EL3 has a new bit NMEA which disables the masking of SError
>     interrupts by PSTATE.A when the SError interrupt is taken to EL3.
>     For QEMU we only need to make the bit writable, because we have no
>     sources of SError interrupts.
> 
>   * SCR_EL3 has a new bit EASE which causes synchronous external
>     aborts taken to EL3 to be taken at the same entry point as SError.
>     (Note that this does not mean that they are SErrors for purposes
>     of PSTATE.A masking or that the syndrome register reports them as
>     SErrors: it just means that the vector offset is different.)
> 
>   * The existing SCTLR_EL3.IESB has an effective value of 1 when
>     SCR_EL3.NMEA is 1.  For QEMU this is a no-op because we don't need
>     different behaviour based on IESB (we don't need to do anything to
>     ensure that error exceptions are synchronized).
> 
> So for QEMU the things we need to change are:
>   * Make SCR_EL3.{NMEA,EASE} writable
>   * When taking a synchronous external abort at EL3, adjust the
>     vector entry point if SCR_EL3.EASE is set
>   * Advertise the feature in the ID registers
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
> Based-on:<20220531114258.855804-1-peter.maydell@linaro.org>
> ("target/arm: Declare support for FEAT_RASv1p1")
> 
>   docs/system/arm/emulation.rst |  1 +
>   target/arm/cpu.h              |  5 +++++
>   target/arm/cpu64.c            |  4 ++--
>   target/arm/helper.c           | 36 +++++++++++++++++++++++++++++++++++
>   4 files changed, 44 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~