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([2602:ae:1547:e101:4ae9:ceee:85cc:a70c]) by smtp.gmail.com with ESMTPSA id a31-20020a631a1f000000b003db072fd9adsm10690789pga.74.2022.05.31.09.04.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 May 2022 09:04:43 -0700 (PDT) Message-ID: <28df077d-ba3d-6f37-04c8-e03e2e61fac8@linaro.org> Date: Tue, 31 May 2022 09:04:41 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH] target/arm: Implement FEAT_DoubleFault Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20220531151431.949322-1-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20220531151431.949322-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 5/31/22 08:14, Peter Maydell wrote: > The FEAT_DoubleFault extension adds the following: > > * All external aborts on instruction fetches and translation table > walks for instruction fetches must be synchronous. For QEMU this > is already true. > > * SCR_EL3 has a new bit NMEA which disables the masking of SError > interrupts by PSTATE.A when the SError interrupt is taken to EL3. > For QEMU we only need to make the bit writable, because we have no > sources of SError interrupts. > > * SCR_EL3 has a new bit EASE which causes synchronous external > aborts taken to EL3 to be taken at the same entry point as SError. > (Note that this does not mean that they are SErrors for purposes > of PSTATE.A masking or that the syndrome register reports them as > SErrors: it just means that the vector offset is different.) > > * The existing SCTLR_EL3.IESB has an effective value of 1 when > SCR_EL3.NMEA is 1. For QEMU this is a no-op because we don't need > different behaviour based on IESB (we don't need to do anything to > ensure that error exceptions are synchronized). > > So for QEMU the things we need to change are: > * Make SCR_EL3.{NMEA,EASE} writable > * When taking a synchronous external abort at EL3, adjust the > vector entry point if SCR_EL3.EASE is set > * Advertise the feature in the ID registers > > Signed-off-by: Peter Maydell > --- > Based-on:<20220531114258.855804-1-peter.maydell@linaro.org> > ("target/arm: Declare support for FEAT_RASv1p1") > > docs/system/arm/emulation.rst | 1 + > target/arm/cpu.h | 5 +++++ > target/arm/cpu64.c | 4 ++-- > target/arm/helper.c | 36 +++++++++++++++++++++++++++++++++++ > 4 files changed, 44 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson r~