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To: Chinmay Rath , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, npiggin@gmail.com, danielhb413@gmail.com, harshpb@linux.ibm.com References: <20240607144921.726730-1-rathc@linux.ibm.com> <20240607144921.726730-4-rathc@linux.ibm.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240607144921.726730-4-rathc@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/7/24 07:49, Chinmay Rath wrote: > Moving the following instructions to decodetree specification: > > lxv{b16, d2, h8, w4, ds, ws}x : X-form > stxv{b16, d2, h8, w4}x : X-form > > The changes were verified by validating that the tcg-ops generated for those > instructions remain the same, which were captured using the '-d in_asm,op' flag. > > Signed-off-by: Chinmay Rath > --- > target/ppc/insn32.decode | 10 ++ > target/ppc/translate/vsx-impl.c.inc | 199 ++++++++++++---------------- > target/ppc/translate/vsx-ops.c.inc | 12 -- > 3 files changed, 97 insertions(+), 124 deletions(-) Because the ops are identical, Reviewed-by: Richard Henderson But you really should update these to use tcg_gen_qemu_ld/st_i128 with the proper atomicity flags. This will fix an existing bug... > +static bool trans_LXVD2X(DisasContext *ctx, arg_LXVD2X *a) > { > TCGv EA; > TCGv_i64 t0; > + > + REQUIRE_VSX(ctx); > + REQUIRE_INSNS_FLAGS2(ctx, VSX); > + > t0 = tcg_temp_new_i64(); > gen_set_access_type(ctx, ACCESS_INT); > + EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); > gen_qemu_ld64_i64(ctx, t0, EA); > + set_cpu_vsr(a->rt, t0, true); where the vector register is partially modified ... > tcg_gen_addi_tl(EA, EA, 8); > gen_qemu_ld64_i64(ctx, t0, EA); before a fault from the second load is recognized. Similarly for stores leaving memory partially modified. r~