From: Richard Henderson <richard.henderson@linaro.org>
To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Kito Cheng <kito.cheng@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Subject: Re: [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros
Date: Wed, 16 Dec 2020 09:21:55 -0600 [thread overview]
Message-ID: <29339dfc-e9c4-20ee-8c26-63921083571b@linaro.org> (raw)
In-Reply-To: <20201216020150.3157-3-frank.chang@sifive.com>
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> From: Kito Cheng <kito.cheng@sifive.com>
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
> target/riscv/insn32-64.decode | 4 +++
> target/riscv/insn32.decode | 7 +++-
> target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++++++++++++++++++++
> target/riscv/translate.c | 42 ++++++++++++++++++++++
> 4 files changed, 99 insertions(+), 1 deletion(-)
> create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ori_i64(ret, arg1, MAKE_64BIT_MASK(32, 32));
> + tcg_gen_ctzi_i64(ret, ret, 32);
> +}
One nit: use clzi_i64(ret, ret, 64).
Most hosts, including x86_64, naturally return the register width for zero. If
you use something else, like this, then tcg will generate an extra comparison
and conditional move.
In this case you know that zero is impossible, because you just set all of the
high 32 bits, but that knowledge won't be present in the expansion of ctzi.
r~
next prev parent reply other threads:[~2020-12-16 15:25 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-16 2:01 [RFC v2 00/15] support subsets of bitmanip extension frank.chang
2020-12-16 2:01 ` [RFC v2 01/15] target/riscv: reformat @sh format encoding for B-extension frank.chang
2020-12-16 15:15 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 02/15] target/riscv: rvb: count leading/trailing zeros frank.chang
2020-12-16 15:21 ` Richard Henderson [this message]
2020-12-16 2:01 ` [RFC v2 03/15] target/riscv: rvb: count bits set frank.chang
2020-12-16 15:24 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 04/15] target/riscv: rvb: logic-with-negate frank.chang
2020-12-16 15:25 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 05/15] target/riscv: rvb: pack two words into one register frank.chang
2020-12-16 16:23 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 06/15] target/riscv: rvb: min/max instructions frank.chang
2020-12-16 16:23 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 07/15] target/riscv: rvb: sign-extend instructions frank.chang
2020-12-16 16:25 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 08/15] target/riscv: rvb: single-bit instructions frank.chang
2020-12-16 16:34 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 09/15] target/riscv: rvb: shift ones frank.chang
2020-12-16 16:35 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 10/15] target/riscv: rvb: rotate (left/right) frank.chang
2020-12-16 16:39 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 11/15] target/riscv: rvb: generalized reverse frank.chang
2020-12-16 16:52 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 12/15] target/riscv: rvb: generalized or-combine frank.chang
2020-12-16 18:15 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 13/15] target/riscv: rvb: address calculation frank.chang
2020-12-16 18:17 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend frank.chang
2020-12-16 18:30 ` Richard Henderson
2020-12-16 2:01 ` [RFC v2 15/15] target/riscv: rvb: support and turn on B-extension from command line frank.chang
2020-12-16 9:14 ` Kito Cheng
2020-12-16 18:31 ` Richard Henderson
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