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References: <CAHgzvFi2wjPtJzU9hXzdaZsbYr085VCbjfsiUeVc5XnUR8arHw@mail.gmail.com>
From: Laurent Vivier <lvivier@redhat.com>
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Date: Thu, 8 Dec 2016 08:50:40 +0100
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Subject: Re: [Qemu-devel] [Qemu-trivial] [PATCH] cadence_uart: Check if
 receiver timeout counter is disabled
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To: Andrew Gacek <andrew.gacek@gmail.com>, qemu-devel@nongnu.org, qemu-trivial@nongnu.org, "Edgar E. Iglesias\"" <edgar.iglesias@gmail.com>, Alistair Francis <alistair.francis@xilinx.com>, qemu-arm@nongnu.org

I CC: Xilinx Zynq Maintainers.

Laurent

On 07/12/2016 22:12, Andrew Gacek wrote:
> When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to
> 0, the receiver timeout counter should be disabled. See page 1801 of
> "Zynq-7000 AP SoC Technical Reference Manual". This commit adds a
> such a check before setting the receive timeout interrupt.
> 
> Signed-off-by: Andrew Gacek <andrew.gacek@gmail.com>
> ---
>  hw/char/cadence_uart.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> index 0215d65..54194b1 100644
> --- a/hw/char/cadence_uart.c
> +++ b/hw/char/cadence_uart.c
> @@ -138,7 +138,9 @@ static void fifo_trigger_update(void *opaque)
>  {
>      CadenceUARTState *s = opaque;
> 
> -    s->r[R_CISR] |= UART_INTR_TIMEOUT;
> +    if (s->r[R_RTOR]) {
> +        s->r[R_CISR] |= UART_INTR_TIMEOUT;
> +    }
> 
>      uart_update_status(s);
>  }
>