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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Tue, 26 Jun 2018 07:08:41 -0700
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Subject: Re: [Qemu-devel] [PATCH v5 07/35] target/arm: Implement SVE FP
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>

On 06/25/2018 08:32 AM, Peter Maydell wrote:
>> +# SVE floating-point multiply-accumulate writing addend
>> +FMLA_zpzzz      01100101 .. 1 ..... 000 ... ..... .....         @rda_pg_rn_rm
>> +FMLS_zpzzz      01100101 .. 1 ..... 001 ... ..... .....         @rda_pg_rn_rm
>> +FNMLA_zpzzz     01100101 .. 1 ..... 010 ... ..... .....         @rda_pg_rn_rm
>> +FNMLS_zpzzz     01100101 .. 1 ..... 011 ... ..... .....         @rda_pg_rn_rm
>> +
>> +# SVE floating-point multiply-accumulate writing multiplicand
>> +# FMAD, FMSB, FNMAD, FNMS
>> +FMLA_zpzzz      01100101 .. 1 ..... 100 ... ..... .....         @rdn_pg_rm_ra
>> +FMLS_zpzzz      01100101 .. 1 ..... 101 ... ..... .....         @rdn_pg_rm_ra
>> +FNMLA_zpzzz     01100101 .. 1 ..... 110 ... ..... .....         @rdn_pg_rm_ra
>> +FNMLS_zpzzz     01100101 .. 1 ..... 111 ... ..... .....         @rdn_pg_rm_ra
> It's not clear to me how we can implement both of these groups
> with the same functions. Some commentary might help.

Note the different decode: @rda_pg_rn_rm vs @rdn_pg_rm_ra.
The same sets of arguments are filled in from different fields
in the instruction.


r~