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[213.30.8.110]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a1f5a4bbf0sm21633059f8f.82.2025.05.15.01.10.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 May 2025 01:10:46 -0700 (PDT) Message-ID: <29536f13-b441-4cb4-a58e-831c008a0962@linaro.org> Date: Thu, 15 May 2025 09:10:43 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20250425152311.804338-1-richard.henderson@linaro.org> <20250425152311.804338-8-richard.henderson@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/14/25 22:33, Daniel Henrique Barboza wrote: > Richard, > > On 4/25/25 12:23 PM, Richard Henderson wrote: >> Do not examine a random host return address, but >> properly compute the next pc for the guest cpu. >> >> Fixes: f18637cd611 ("RISC-V: Add misa runtime write support") >> Signed-off-by: Richard Henderson >> --- >>   target/riscv/csr.c | 22 +++++++++++++++++----- >>   1 file changed, 17 insertions(+), 5 deletions(-) >> >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >> index a663f527a4..85f9b4c3d2 100644 >> --- a/target/riscv/csr.c >> +++ b/target/riscv/csr.c >> @@ -30,6 +30,8 @@ >>   #include "exec/icount.h" >>   #include "qemu/guest-random.h" >>   #include "qapi/error.h" >> +#include "tcg/insn-start-words.h" >> +#include "internals.h" >>   #include >>   /* CSR function table public API */ >> @@ -2099,6 +2101,19 @@ static RISCVException read_misa(CPURISCVState *env, int csrno, >>       return RISCV_EXCP_NONE; >>   } >> +static target_ulong get_next_pc(CPURISCVState *env, uintptr_t ra) >> +{ >> +    uint64_t data[TARGET_INSN_START_WORDS]; > > Isn't this 'INSN_START_WORDS'?  I'm seeing code in i386 that is similar > to what we're doing here and it's using INSN_START_WORDS: Yes, though INSN_START_WORDS is a very recent change. Probably the week after I posted this patch set. :-) r~