From: Richard Henderson <richard.henderson@linaro.org>
To: Joelle van Dyne <j@getutm.app>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH v2 18/19] tcg/aarch64: Implement flush_idcache_range manually
Date: Sun, 1 Nov 2020 07:09:16 -0800 [thread overview]
Message-ID: <29b4f60b-bc5e-d966-7913-9f64cc8b4006@linaro.org> (raw)
In-Reply-To: <CA+E+eSB64cm8GPsuEYNQJLkF2gPiF2oueYPOOTtxpYy7hWzTRg@mail.gmail.com>
On 10/31/20 6:25 PM, Joelle van Dyne wrote:
> Another thing, for x86 (and maybe other archs), the icache is cache
> coherent but does it apply if we are aliasing the memory address? I
> think in that case, it's like we're doing a DMA right and still need
> to do flushing+invalidating?
No, it is not like dma. The x86 caches are physically tagged, so virtual
aliasing does not matter.
r~
next prev parent reply other threads:[~2020-11-01 15:10 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-30 0:49 [PATCH v2 00/19] Mirror map JIT memory for TCG Richard Henderson
2020-10-30 0:49 ` [PATCH v2 01/19] tcg: Enhance flush_icache_range with separate data pointer Richard Henderson
2020-11-01 6:54 ` Joelle van Dyne
2020-11-03 23:02 ` Richard Henderson
2020-10-30 0:49 ` [PATCH v2 02/19] tcg: Move tcg prologue pointer out of TCGContext Richard Henderson
2020-10-30 0:49 ` [PATCH v2 03/19] tcg: Move tcg epilogue " Richard Henderson
2020-10-30 0:49 ` [PATCH v2 04/19] tcg: Introduce tcg_mirror_rw_to_rx/tcg_mirror_rx_to_rw Richard Henderson
2020-10-30 0:49 ` [PATCH v2 05/19] tcg: Adjust tcg_out_call for const Richard Henderson
2020-10-30 0:49 ` [PATCH v2 06/19] tcg: Adjust tcg_out_label " Richard Henderson
2020-10-30 0:49 ` [PATCH v2 07/19] tcg: Adjust tcg_register_jit " Richard Henderson
2020-10-30 0:49 ` [PATCH v2 08/19] tcg: Adjust tb_target_set_jmp_target for split rwx Richard Henderson
2020-10-30 0:49 ` [PATCH v2 09/19] tcg: Make DisasContextBase.tb const Richard Henderson
2020-10-30 0:49 ` [PATCH v2 10/19] tcg: Make tb arg to synchronize_from_tb const Richard Henderson
2020-10-30 0:49 ` [PATCH v2 11/19] tcg: Use Error with alloc_code_gen_buffer Richard Henderson
2020-10-30 0:49 ` [PATCH v2 12/19] tcg: Add --accel tcg,split-rwx property Richard Henderson
2020-10-30 0:49 ` [PATCH v2 13/19] accel/tcg: Support split-rwx for linux with memfd Richard Henderson
2020-10-30 0:49 ` [PATCH v2 14/19] RFC: accel/tcg: Support split-rwx for darwin/iOS with vm_remap Richard Henderson
2020-11-01 1:42 ` Joelle van Dyne
2020-11-01 21:11 ` Joelle van Dyne
2020-10-30 0:49 ` [PATCH v2 15/19] tcg: Return the rx mirror of TranslationBlock from exit_tb Richard Henderson
2020-10-30 0:49 ` [PATCH v2 16/19] tcg/i386: Support split-rwx code generation Richard Henderson
2020-10-30 0:49 ` [PATCH v2 17/19] tcg/aarch64: Use B not BL for tcg_out_goto_long Richard Henderson
2020-10-30 0:49 ` [PATCH v2 18/19] tcg/aarch64: Implement flush_idcache_range manually Richard Henderson
2020-11-01 1:25 ` Joelle van Dyne
2020-11-01 15:09 ` Richard Henderson [this message]
2020-11-03 23:08 ` Richard Henderson
2020-10-30 0:49 ` [PATCH v2 19/19] tcg/aarch64: Support split-rwx code generation Richard Henderson
2020-10-30 1:27 ` [PATCH v2 00/19] Mirror map JIT memory for TCG no-reply
2020-10-30 18:26 ` Paolo Bonzini
2020-10-30 18:57 ` Richard Henderson
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