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Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler Content-Language: en-US To: Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson , Zhiwei Liu Cc: Weiwei Li , Daniel Henrique Barboza References: <20230530131843.1186637-1-christoph.muellner@vrull.eu> <20230530131843.1186637-7-christoph.muellner@vrull.eu> From: LIU Zhiwei In-Reply-To: <20230530131843.1186637-7-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=baxiantai@gmail.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.093, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2023/5/30 21:18, Christoph Muellner wrote: > From: Christoph Müllner > > The disassembler needs the available extensions in order > to properly decode instructions in case of overlapping > encodings (e.g. for vendor extensions). > > Let's use the field 'disassemble_info::private_data' to store > our RISCVCPUConfig pointer. > > Signed-off-by: Christoph Müllner > --- > target/riscv/cpu.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 5b7818dbd1..6f0cd9a0bb 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -819,6 +819,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > { > RISCVCPU *cpu = RISCV_CPU(s); > CPURISCVState *env = &cpu->env; > + RISCVCPUConfig *cfg = &cpu->cfg; > + > + info->private_data = cfg; I don't know if this field will be overridden by the binutils. Can we extend the struct disassemble_info, and add some fields like supporting for Capstone? Zhiwei > > switch (env->xl) { > case MXL_RV32: