From: Jan Bobek <jan.bobek@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [RISU RFC PATCH v1 1/7] risugen_common: add insnv, randint_constr, rand_fill
Date: Fri, 28 Jun 2019 11:10:26 -0400 [thread overview]
Message-ID: <29d1496f-5688-0bbb-812e-088b04018159@gmail.com> (raw)
In-Reply-To: <ba5161d6-5c31-fe9e-5079-04550333776d@linaro.org>
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On 6/27/19 4:53 AM, Richard Henderson wrote:
> On 6/19/19 7:04 AM, Jan Bobek wrote:
>> + my $value = ($args{bigendian}
>> + ? ($args{value} >> (8 * $args{len} - $bitlen))
>> + : $args{value});
> ...
>> + $args{value} >>= $bitlen unless $args{bigendian};
>
> I think this could be clearer without modifying $args.
> I mis-read these the first time around.
>
> Perhaps
>
> my $bitpos = 0;
> my $bitend = 8 * $args{len};
> while ($bitpos < $bitend) {
> ...
> my $value = $args{value} >> ($args{bigendian}
> ? $bitend - $bitpos - $bitlen
> : $bitpos);
> ...
> $bitpos += $bitlen;
> }
Looks good, I'll change it.
>> +sub randint_constr(%)
>> +{
>> + my (%args) = @_;
>> + my $bitlen = $args{bitlen};
>> + my $halfrange = 1 << ($bitlen - 1);
>> +
>> + while (1) {
>> + my $value = int(rand(2 * $halfrange));
>> + $value -= $halfrange if defined $args{signed} && $args{signed};
>> + $value &= ~$args{fixedbitmask} if defined $args{fixedbitmask};
>> + $value |= $args{fixedbits} if defined $args{fixedbits};
>> +
>> + if (defined $args{constraint}) {
>> + if (!($args{constraint} >> 63)) {
>> + $value = $args{constraint};
>> + } elsif ($value == ~$args{constraint}) {
>> + next;
>> + }
>> + }
>
> I don't understand what you're doing here with {constraint}.
> Some additional commentary would help.
The idea is: if the most significant bit of $args{constraint} is zero,
$args{constraint} is the value we want to return; if the most
significant bit is one, ~$args{constraint} (its bit inversion) is the
value we want to *avoid*, so we try again. This is used to to
implement constraints on fields such as
MOVLPS SSE 00001111 0001001 d !emit { modrm(mod => ~MOD_DIRECT); mem(size => 8); }
MOVLHPS SSE 00001111 00010110 !emit { modrm(mod => MOD_DIRECT); }
The bitshift by 63 assumes 64-bit integers, but that assumption is
present in other places, too. I couldn't think of a better way to do
it: comparing it to zero doesn't work because the value is unsigned.
I will include a comment explaining this in v2, unless you have
other suggestions.
-Jan
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next prev parent reply other threads:[~2019-06-28 15:38 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-19 5:04 [Qemu-devel] [RISU RFC PATCH v1 0/7] Support for generating x86 SSE/SSE2 test images Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 1/7] risugen_common: add insnv, randint_constr, rand_fill Jan Bobek
2019-06-27 8:53 ` Richard Henderson
2019-06-28 15:10 ` Jan Bobek [this message]
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 2/7] risugen_x86_asm: add module Jan Bobek
2019-06-27 9:05 ` Richard Henderson
2019-06-28 15:57 ` Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 3/7] risugen_x86_emit: " Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 4/7] risugen_x86: " Jan Bobek
2019-06-27 10:29 ` Richard Henderson
2019-06-27 10:53 ` Richard Henderson
2019-06-28 16:03 ` Jan Bobek
2019-06-28 17:06 ` Jan Bobek
2019-06-29 12:03 ` Richard Henderson
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 5/7] risugen: allow all byte-aligned instructions Jan Bobek
2019-06-27 10:30 ` Richard Henderson
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 6/7] x86.risu: add SSE instructions Jan Bobek
2019-06-19 5:04 ` [Qemu-devel] [RISU RFC PATCH v1 7/7] x86.risu: add SSE2 instructions Jan Bobek
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